Energy efficient torus networks with on/off links

[EN] Future exascale computing systems will require energy and performance efficient interconnection networks to respond to the high data movement demands of new applications, such as those coming from big-data and artificial intelligence areas. The network structure plays a major role in the overall interconnect performance, for this reason torus is a common topology used in the current largest supercomputers. There are several proposals to improve energy efficiency of interconnection networks. However, few works combine both energy and performance, and sometimes they are treated as opposed issues. In this paper, we try to determine which torus network configuration offers the best performance/energy ratio when high-radix switches are used to build the interconnect system. The performance/energy evaluation has been performed by trace-driven simulation under realistic scenarios, where several mixes of scientific applications share a supercomputer system and are scheduled to be executed with the available resources at each moment.This work has been supported by the Spanish MINECO and European Commission (FEDER funds) under project TIN2015-66972-05-1-R and project TIN2015-66972-05-2-R. Francisco J. Andujar is also funded by the Spanish MINECO under a Juan de la Cierva grant FJCI-2015-26080.Andújar, FJ.; Coll, S.; Alonso Díaz, M.; Martínez-Rubio, J.; López Rodríguez, PJ.; Sánchez, JL.; Alfaro, FJ.... (2019). Energy efficient torus networks with on/off links. Journal of Parallel and Distributed Computing. 130:37-49. https://doi.org/10.1016/j.jpdc.2019.03.015S374913

Power consumption optimization and delay based on ant colony algorithm in network-on-chip

With a further increase of the number of on-chip devices, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new NoC structure to solve the interconnection of an on-chip device. For the purpose of improving the performance of a network-on-chip without a significant increase in power consumption, the paper proposes a network-on-chip that selects NoC (Network-On-Chip) platform with 2-dimension mesh as the carrier and incorporates communication power consumption and delay into a unified cost function. The paper uses ant colony optimization for the realization of NoC map facing power consumption and delay potential. The experiment indicates that in comparison with a random map, single objective optimization can separately account for (30%~47%) and (20%~39%) of communication power consumption and execution time, and joint objective optimization can further excavate the potential of time dimension in a mapping scheme dominated by the power

Using Proportional-Integral-Differential approach for Dynamic Traffic Prediction in Wireless Network-on-Chip

The massive integration of cores in multi-core system has enabled chip designer to design systems while meeting the power performance demands of the applications. Wireless interconnection has emerged as an energy efficient solution to the challenges of multi-hop communication over the wireline paths in conventional Networks-on-Chips (NoCs). However, to ensure the full benefits of this novel interconnect technology, design of simple, fair and efficient Medium Access Control (MAC) mechanism to grant access to the on-chip wireless communication channel is needed. Moreover, to adapt to the varying traffic demands from the applications running on a multicore environment, MAC mechanisms should dynamically adjust the transmission slots of the wireless interfaces (WIs). To ensure an efficient utilization of the wireless medium in a Wireless NoC (WiNoC), in this work we present the design of prediction model that is used by two dynamic MAC mechanism to predict the traffic demand of the WIs and respond accordingly by adjusting transmission slots of the WIs. Through system level simulations, we show that the traffic aware MAC mechanisms are more energy efficient as well as capable of sustaining higher data bandwidth in WiNoCs

Combined Dynamic Thermal Management Exploiting Broadcast-Capable Wireless Network-on-Chip Architecture

With the continuous scaling of device dimensions, the number of cores on a single die is constantly increasing. This integration of hundreds of cores on a single die leads to high power dissipation and thermal issues in modern Integrated Circuits (ICs). This causes problems related to reliability, timing violations and lifetime of electronic devices. Dynamic Thermal Management (DTM) techniques have emerged as potential solutions that mitigate the increasing temperatures on a die. However, considering the scaling of system sizes and the adoption of the Network-on-Chip (NoC) paradigm to serve as the interconnection fabric exacerbates the problem as both cores and NoC elements contribute to the increased heat dissipation on the chip. Typically, DTM techniques can either be proactive or reactive. Proactive DTM techniques, where the system has the ability to predict the thermal profile of the chip ahead of time are more desirable than reactive DTM techniques where the system utilizes thermal sensors to determine the current temperature of the chip. Moreover, DTM techniques either address core or NoC level thermal issues separately. Hence, this thesis proposes a combined proactive DTM technique that integrates both core level and NoC level DTM techniques. The combined DTM mechanism includes a dynamic temperature-aware routing approach for the NoC level elements, and includes task reallocation heuristics for the core level elements. On-chip wireless interconnects recently envisioned to enable energy-efficient data exchange between cores in a multicore chip will be used to provide a broadcast-capable medium to efficiently distribute thermal control messages to trigger and manage the DTM. Combining the proactive DTM technique with on-chip wireless interconnects, the on-chip temperature is restricted within target temperatures without significantly affecting the performance of the NoC based interconnection fabric of the multicore chip

Artificial Neural Network Based Prediction Mechanism for Wireless Network on Chips Medium Access Control

As per Moore’s law, continuous improvement over silicon process technologies has made the integration of hundreds of cores on to a single chip possible. This has resulted in the paradigm shift towards multicore and many-core chips where, hundreds of cores can be integrated on the same die and interconnected using an on-chip packet-switched network called a Network-on-Chip (NoC). Various tasks running on different cores generate different rates of communication between pairs of cores. This lead to the increase in spatial and temporal variation in the workloads, which impact the long distance data communication over multi-hop wire line paths in conventional NoCs. Among different alternatives, due to the CMOS compatibility and energy-efficiency, low-latency wireless interconnects operating in the millimeter wave (mm-wave) band is nearer term solution to this multi-hop communication problem in traditional NoCs. This has led to the recent exploration of millimeter-wave (mm-wave) wireless technologies in wireless NoC architectures (WiNoC). In a WiNoC, the mm-wave wireless interconnect is realized by equipping some NoC switches with an wireless interface (WI) that contains an antenna and transceiver circuit tuned to operate in the mm-wave frequency. To enable collision free and energy-efficient communication among the WIs, the WIs is also equipped with a medium access control mechanism (MAC) unit. Due to the simplicity and low-overhead implementation, a token passing based MAC mechanism to enable Time Division Multiple Access (TDMA) has been adopted in many WiNoC architectures. However, such simple MAC mechanism is agnostic of the demand of the WIs. Based on the tasks mapped on a multicore system the demand through the WIs can vary both spatially and temporally. Hence, if the MAC is agnostic of such demand variation, energy is wasted when no flit is transferred through the wireless channel. To efficiently utilize the wireless channel, MAC mechanisms that can dynamically allocate token possession period of the WIs have been explored in recent time for WiNoCs. In the dynamic MAC mechanism, a history-based prediction is used to predict the bandwidth demand of the WIs to adjust the token possession period with respect to the traffic variation. However, such simple history based predictors are not accurate and limits the performance gain due to the dynamic MACs in a WiNoC. In this work, we investigate the design of an artificial neural network (ANN) based prediction methodology to accurately predict the bandwidth demand of each WI. Through system level simulation, we show that the dynamic MAC mechanisms enabled with the ANN based prediction mechanism can significantly improve the performance of a WiNoC in terms of peak bandwidth, packet energy and latency compared to the state-of-the-art dynamic MAC mechanisms