468 research outputs found
Concatenated Turbo/LDPC codes for deep space communications: performance and implementation
Deep space communications require error correction codes able to reach extremely low bit-error-rates, possibly with a steep waterfall region and without error floor. Several schemes have been proposed in the literature to achieve these goals. Most of them rely on the concatenation of different codes that leads to high hardware implementation complexity and poor resource sharing. This work proposes a scheme based on the concatenation of non-custom LDPC and turbo codes that achieves excellent error correction performance. Moreover, since both LDPC and turbo codes can be decoded with the BCJR algorithm, our preliminary results show that an efficient hardware architecture with high resource reuse can be designe
Spatially Coupled Codes and Optical Fiber Communications: An Ideal Match?
In this paper, we highlight the class of spatially coupled codes and discuss
their applicability to long-haul and submarine optical communication systems.
We first demonstrate how to optimize irregular spatially coupled LDPC codes for
their use in optical communications with limited decoding hardware complexity
and then present simulation results with an FPGA-based decoder where we show
that very low error rates can be achieved and that conventional block-based
LDPC codes can be outperformed. In the second part of the paper, we focus on
the combination of spatially coupled LDPC codes with different demodulators and
detectors, important for future systems with adaptive modulation and for
varying channel characteristics. We demonstrate that SC codes can be employed
as universal, channel-agnostic coding schemes.Comment: Invited paper to be presented in the special session on "Signal
Processing, Coding, and Information Theory for Optical Communications" at
IEEE SPAWC 201
VLSI implementation of a multi-mode turbo/LDPC decoder architecture
Flexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, reconfigurable architectures for the physical layer are an attractive solution not only to switch among different coding modes but also to achieve interoperability. This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding. The novel contributions of this paper are: i) tackling the reconfiguration issue introducing a formal and systematic treatment that, to the best of our knowledge, was not previously addressed; ii) proposing a reconfigurable NoCbased turbo/LDPC decoder architecture and showing that wide flexibility can be achieved with a small complexity overhead. Obtained results show that dynamic switching between most of considered communication standards is possible without pausing the decoding activity. Moreover, post-layout results show that tailoring the proposed architecture to the WiMAX standard leads to an area occupation of 2.75 mm2 and a power consumption of 101.5 mW in the worst case
Research on high performance LDPC decoder
制度:新 ; 報告番号:甲3272号 ; 学位の種類:博士(工学) ; 授与年月日:2011/3/15 ; 早大学位記番号:新557
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