Leveraging CMOS Aging for Efficient Microelectronics Design

Aging is known to impact electronic systems affecting performance and reliability. However, it has been shown that it also brings benefits for power saving and area optimization. This paper presents highlights of those benefits and further shows how aging effects can be leveraged by novel methods to contribute towards improving hardware oriented security and reliability of electronic circuits. We have demonstrated static power reduction in complex circuits from IWLS05 benchmark suite, reaching a noticeable 7S% of reduction in ten years of operation. In hardware oriented security, a novel aging sensor has been proposed for detection of recycled ICs, measuring discharge time Tdv of the virtual power (VV dd ) network in power-gated designs. This sensor utilizes discharge time of VV dd network through leakage current that is much more sensitive to aging than path delay, exhibiting up to 15.7X increment in 10 years. Furthermore, we show how frequency degradation caused by aging is used for online prediction of remaining useful lifetime (RUL) of electronic circuits. Results show an average RUL prediction deviation of less than 0.1 years. This methodology provides node calculations rather than a mean time to failure (MTTF) of the population. The set of techniques that are presented in this paper takes advantage of aging effects, having a positive impact in various aspects of microelectronic systems

Quantifiable Assurance: From IPs to Platforms

Hardware vulnerabilities are generally considered more difficult to fix than software ones because they are persistent after fabrication. Thus, it is crucial to assess the security and fix the vulnerabilities at earlier design phases, such as Register Transfer Level (RTL) and gate level. The focus of the existing security assessment techniques is mainly twofold. First, they check the security of Intellectual Property (IP) blocks separately. Second, they aim to assess the security against individual threats considering the threats are orthogonal. We argue that IP-level security assessment is not sufficient. Eventually, the IPs are placed in a platform, such as a system-on-chip (SoC), where each IP is surrounded by other IPs connected through glue logic and shared/private buses. Hence, we must develop a methodology to assess the platform-level security by considering both the IP-level security and the impact of the additional parameters introduced during platform integration. Another important factor to consider is that the threats are not always orthogonal. Improving security against one threat may affect the security against other threats. Hence, to build a secure platform, we must first answer the following questions: What additional parameters are introduced during the platform integration? How do we define and characterize the impact of these parameters on security? How do the mitigation techniques of one threat impact others? This paper aims to answer these important questions and proposes techniques for quantifiable assurance by quantitatively estimating and measuring the security of a platform at the pre-silicon stages. We also touch upon the term security optimization and present the challenges for future research directions

Investigating and Leveraging EM and Backscattering Side Channels for Hardware Security

This dissertation is focused on investigating and leveraging side-channel leakage for hardware security. To help designers address and take advantage of electromagnetic (EM) side channels, two methods for locating the physical sources of EM side channels have been developed. Both methods are used to investigate how the EM side-channel sources change with frequency and program activity. The second half of this dissertation introduces two methods that use side channels for component authentication. The same properties that make side channels such a threat, also make them useful for authenticating electronic components. The first method uses EM side channels for identifying integrated circuits (ICs) installed on a device. Focusing on components already integrated onto a device lets designers authenticate devices assembled by third parties. The second method uses the recently defined backscattering side channel for detecting recycled ICs. Unlike other types of side channels, backscattering is directly affected by the IC aging. Since the backscattering side channel is nondestructive and requires no additional circuitry on the IC, it is low cost. The effect of aging on the side channel is then investigated through simulation and experimentation.Ph.D

Secure Physical Design

An integrated circuit is subject to a number of attacks including information leakage, side-channel attacks, fault-injection, malicious change, reverse engineering, and piracy. Majority of these attacks take advantage of physical placement and routing of cells and interconnects. Several measures have already been proposed to deal with security issues of the high level functional design and logic synthesis. However, to ensure end-to-end trustworthy IC design flow, it is necessary to have security sign-off during physical design flow. This paper presents a secure physical design roadmap to enable end-to-end trustworthy IC design flow. The paper also discusses utilization of AI/ML to establish security at the layout level. Major research challenges in obtaining a secure physical design are also discussed

Performance Improvement of the Inertial Sensors of Advanced Virgo Seismic Isolators with Digital Techniques

Gravitational waves, predicted on the basis of the General Relativity, are ripples in the curvature of space-time that propagate as a wave. The passage of a gravitational wave induces tiny oscillations in the relative separation between two test masses, that can be measured. Nevertheless these oscillations are extremely small, so that only a very sensitive detector is able to measure them. The Advanced Virgo project is a major upgrade of the 3 km-long interferometric gravitational wave detector Virgo, with the goal of increasing its sensitivity by about one order of magnitude in the whole detection band. We expect to have a maximum strain amplitude sensitivity of 4 × 10^−24 1/√Hz at ∼ 300 Hz. In other words this means that it will be able to detect a relative displacement between mirrors of about 10^−20 m, by averaging for one second. This sensitivity should allow to detect several tens of events per year. Among the various ongoing updates, an important improvement is represented by the new electronics used to control the Superattenuators, complex mechanical structures that isolate optical elements from seismic noise by a factor 10^15 at 1 Hz. Using the information of several inertial sensors, a digital control system keeps the structures as stable as possible. A new board for the Superattenuator control has been designed, that incorporates analog-to-digital and digital-to-analog converters, a Field Programmable Gate Array (FPGA) and a Digital Signal Processor (DSP) into a single unit. This board is enough to handle every single part of the Superattenuator inertial control. It performs the computation of feedback forces, and is used to synthesize sine wave to drive the coils of the inertial sensors, as well as to read their output. Furthermore it interfaces with all the other structures of Virgo. In this thesis I have studied the horizontal accelerometers, feedback-controlled sensors used in the Superattenuator inertial control to measure the seismic noise in the frequency band from DC to 100 Hz. Using the computing power of the new electronics (the new DSP has 8 cores and can compute 8.4 GFLOPS per core for double precision floating point indeed), I have designed a new control system for the accelerometers, exploiting the properties of a critically damped harmonic oscillator. This system allows to improve by about one order of magnitude the sensitivity of these sensors, with respect to the system used in Virgo, by reducing the root mean square of the force needed for the control by a factor 2. In this way, the accelerometer sensitivity can reach about 10^−9 (m/s^2)/√Hz at 1 Hz. In the last part of the thesis I have studied the Linear Variable Differential Transformer (LVDT), a kind of displacement sensor widely used in Superattenuator control. I have designed a system to read the output of LVDT using a FPGA. It consists of a Direct Digital Synthesizer (DDS) that is used both to drive the primary coil of the LVDT with a sine wave at 50 kHz, and then to demodulate the signal induced on the secondary coils, whose amplitude is modulated by a signal proportional to displacement. An algorithm, based on a Phase-Locked Loop (PLL), allows the detection of the phase shift of the signal induced on the secondary coils, and tunes the system in order to maximize the signal-to-noise ratio of the measurement of displacement

Reflective-Physically Unclonable Function based System for Anti-Counterfeiting

Physically unclonable functions (PUF) are physical security mechanisms, which utilize inherent randomness in processes used to instantiate physical objects. In this dissertation, an extensive overview of the state of the art in implementations, accompanying definitions and their analysis is provided. The concept of the reflective-PUF is presented as a product security solution. The viability of the concept, its evaluation and the requirements of such a system is explored

Computationally efficient algorithms and implementations of adaptive deep brain stimulation systems for Parkinson's disease

Clinical deep brain stimulation (DBS) is a tool used to mitigate pharmacologically intractable neurodegenerative diseases such as Parkinson's disease (PD), tremor and dystonia. Present implementations of DBS use continuous, high frequency voltage or current pulses so as to mitigate PD. This results in some limitations, among which there is stimulation induced side effects and shortening of pacemaker battery life. Adaptive DBS (aDBS) can be used to overcome a number of these limitations. Adaptive DBS is intended to deliver stimulation precisely only when needed. This thesis presents work undertaken to investigate, propose and develop novel algorithms and implementations of systems for adapting DBS. This thesis proposes four system implementations that could facilitate DBS adaptation either in the form of closed-loop DBS or spatial adaptation. The first method involved the use of dynamic detection to track changes in local field potentials (LFP) which can be indicative of PD symptoms. The work on dynamic detection included the synthesis of validation dataset using mainly autoregressive moving average (ARMA) models to enable the evaluation of a subset of PD detection algorithms for accuracy and complexity trade-offs. The subset of algorithms consisted of feature extraction (FE), dimensionality reduction (DR) and dynamic pattern classification stages. The combination with the best trade-off in terms of accuracy and complexity consisted of discrete wavelet transform (DWT) for FE, maximum ratio method (MRM) for DR and k-nearest neighbours (k-NN) for classification. The MRM is a novel DR method inspired by Fisher's separability criterion. The best combination achieved accuracy measures: F1-score of 97.9%, choice probability of 99.86% and classification accuracy of 99.29%. Regarding complexity, it had an estimated microchip area of 0.84 mm² for estimates in 90 nm CMOS process. The second implementation developed the first known PD detection and monitoring processor. This was achieved using complementary detection, which presents a hardware-efficient method of implementing a PD detection processor for monitoring PD progression in Parkinsonian patients. Complementary detection is achieved by using a combination of weak classifiers to produce a classifier with a higher consistency and confidence level than the individual classifiers in the configuration. The PD detection processor using the same processing stages as the first implementation was validated on an FPGA platform. By mapping the implemented design on a 45 nm CMOS process, the most optimal implementation achieved a dynamic power per channel of 2.26 μW and an area per channel of 0.2384 mm². It also achieved mean accuracy measures: Mathews correlation coefficient (MCC) of 0.6162, an F1-score of 91.38%, and mean classification accuracy of 91.91%. The third implementation proposed a framework for adapting DBS based on a critic-actor control approach. This models the relationship between a trained clinician (critic) and a neuro-modulation system (actor) for modulating DBS. The critic was implemented and validated using machine learning models, and the actor was implemented using a fuzzy controller. Therapy is modulated based on state estimates obtained through the machine learning models. PD suppression was achieved in seven out of nine test cases. The final implementation introduces spatial adaptation for aDBS. Spatial adaptation adjusts to variation in lead position and/or stimulation focus, as poor stimulation focus has been reported to affect therapeutic benefits of DBS. The implementation proposes dynamic current steering systems as a power-efficient implementation for multi-polar multisite current steering, with a particular focus on the output stage of the dynamic current steering system. The output stage uses dynamic current sources in implementing push-pull current sources that are interfaced to 16 electrodes so as to enable current steering. The performance of the output stage was demonstrated using a supply of 3.3 V to drive biphasic current pulses of up to 0.5 mA through its electrodes. The preliminary design of the circuit was implemented in 0.18 μm CMOS technology