Intrinsic Reliability improvement in Biaxially Strained SiGe p-MOSFETs

In this letter we not only show improvement in the performance but also in the reliability of 30nm thick biaxially strained SiGe (20%Ge) channel on Si p-MOSFETs. Compared to Si channel, strained SiGe channel allows larger hole mobility ({\mu}h) in the transport direction and alleviates charge flow towards the gate oxide. {\mu}h enhancement by 40% in SiGe and 100% in Si-cap SiGe is observed compared to the Si hole universal mobility. A ~40% reduction in NBTI degradation, gate leakage and flicker noise (1/f) is observed which is attributed to a 4% increase in the hole-oxide barrier height ({\phi}) in SiGe. Similar field acceleration factor ({\Gamma}) for threshold voltage shift ({\Delta}VT) and increase in noise ({\Delta}SVG) in Si and SiGe suggests identical degradation mechanisms.Comment: 4 figures, 3 pages, accepted for publication in IEEE ED

Reliable time exponents for long term prediction of negative bias temperature instability by extrapolation

To predict the negative bias temperature instability (NBTI) towards the end of pMOSFETs’ 10 years lifetime, power-law based extrapolation is the industrial standard method. The prediction accuracy crucially depends on the accuracy of time exponents, n. The n reported by early work spreads in a wide range and varies with measurement conditions, which can lead to unacceptable errors when extrapolated to 10 years. The objective of this work is to find how to make the n extraction independent of measurement conditions. After removing the contribution from as-grown hole traps (AHT), a new method is proposed to capture the generated defects (GD) in their entirety. The n extracted by this method is around 0.2 and insensitive to measurement conditions for the four fabrication processes we tested. The model based on this method is verified by comparing its prediction with measurements. Under AC operation, the model predicts that GD can contribute to ~90% of NBTI at 10 years

Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

Reduction in static-power dissipation (gate leakage) by using nitrided oxides comes at the expense of enhanced negative-bias temperature instability (NBTI). Therefore, determining the nitrogen content in gate oxides that can simultaneously optimize gate-leakage and NBTI degradation is a problem of significant technological relevance. In this paper, we experimentally and theoretically analyze wide range of gate-leakage and NBTI stress data from a variety of plasma-oxynitride gate dielectric devices to establish an optimization scheme for gate-leakage and NBTI degradation. Calculating electric fields and leakage current both numerically and using simple analytical expressions, we demonstrate a design diagram for arbitrary nitrogen concentration and effective oxide thickness that may be used for process and IC design

ランダム・テレグラフ・ノイズの微細MOSFETへの影響に関する研究

筑波大学 (University of Tsukuba)201

Ab Initio Investigation of Charge Trapping Across the Crystalline- Si -Amorphous- Si O2 Interface

Accurate microscopic description of the charge-trapping process from semiconductor to defects in the dielectric-oxide layer is of paramount importance for understanding many microelectronic devices such as complementary metal-oxide-semiconductor (CMOS) transistors, as well as electrochemical reactions. Unfortunately, most current microscopic descriptions of such processes are based on empirical models with parameters fitted to experimental device performance results or simplified approximations like the Wentzel-Kramers-Brillouin (WKB) method. Some critical questions are still unanswered, including: What controls the charge-hopping rate, the coupling strength between the defect level to semiconductor level, or the energy difference? How does the hopping rate decay with defect-semiconductor distance? What is the fluctuation of the defect level, especially in amorphous dielectrics? Many of these questions can be answered by ab initio calculations. However, to date, there are few ab initio studies for this problem mainly due to technical challenges from atomic-structure construction to large-system calculations. Here, using the latest advances in calculation methods and codes, we study the carrier-trapping problem using density-functional theory (DFT) based on the Heyd-Scuseria-Ernzerhof (HSE) exchange correlation functional. The valence bond random-switching method is used to construct the crystalline-Si-amorphous-SiO2 (c-Si/a-SiO2) interfacial atomic structure, and the HSE yields a band offset that agrees well with experiments. The hopping rate is calculated with the Marcus theory, and the hopping-rate dependences on the gate potential and defect distances are revealed, as well as the range of fluctuation results from amorphous structural variation. We also analyze the result with the simple WKB model and find a major difference in the description of the coupling constant decay with the defect-semiconductor distance. Our results provide the ab initio simulation insights for this important carrier-trapping process for device operation

Development of electrical characterization techniques for lifetime prediction and understanding defects in InGaAs-based III-V transistors

Combining the advanced complementary metal-oxide-semiconductor (CMOS) technique, faster and highly packaged circuits have continuous developing for more than fifty years. During this period time, engineers focus on the higher electrical field and accelerate the degradation to make the highly performance of advanced CMOS devices with better and smaller size than before. At this moment, there are plenty of issues are found which can affect the performances ofthe device. For example, for the new material technique, people prefe tor use III-V materials to instead of the traditional silicon, and for the traditional CMOS device, the main reliability issue is bias temperature instability (BTI), NBTI for pMOS and PBTI for nMOS. Therefore, this thesis will talk about investigating the NBTI/PBTI and III-V device performance and lifetime prediction issues. For the whole ofthe thesis, it can be divided by 4 chapters to describe the details, the first chapter would be the introduction of background knowledge and current understanding for how the traditional CMOS device works, and why the new materials could be instead, like III-V device, it shows the advantages and disadvantages for each of them. Moreover, there are some other information would be explained, such as Discharging-based multiple pulse (DMP) method, and hot carrier stress. Those are also topics and directions relate tod this thesis for the further research. Chapter 2 shows a new measurement method, which called Fast reliability screening technique method (VSS). It compared the conventional measurement method, which is constant voltage stress (CVS), is faster and only use a single device. And it also combined the measurement details and results to show that method is more efficiently, which includes the benefits and parameters discussion in the different conditions. Chapter 3 shows a separation traps method of III-V devices with in In0.53Ga0.47As channel. In this chapter, firstly, it shows the introduction of III-V devices for the basic theory and working function, then there are some experiments, which include both AC and DC measurements to show the III-V devices have very fast recovery abilities. Then because of the recovery ability, the devices would work well after charging and discharging even after heavily stress and long stress time. Moreover, combine the different discharge voltage levels to get the whole border trap energy distribution. After that, the chapter 3 shows how to separate the traps into two different types, type A and type B. there are experiments results and details to show how it is divided. Then it also mentioned the method can work with different stress time, channel thickness and temperature dependence. In Chapter 4, the discussion and a summary about previous work has been given, which also points out the future research plans and directions. It includes the lifetime prediction under slow and fast measurements for III-V devices

Reliability Investigations of MOSFETs using RF Small Signal Characterization

Modern technology needs and advancements have introduced various new concepts such as Internet-of-Things, electric automotive, and Artificial intelligence. This implies an increased activity in the electronics domain of analog and high frequency. Silicon devices have emerged as a cost-effective solution for such diverse applications. As these silicon devices are pushed towards higher performance, there is a continuous need to improve fabrication, power efficiency, variability, and reliability. Often, a direct trade-off of higher performance is observed in the reliability of semiconductor devices. The acceleration-based methodologies used for reliability assessment are the adequate time-saving solution for the lifetime's extrapolation but come with uncertainty in accuracy. Thus, the efforts to improve the accuracy of reliability characterization methodologies run in parallel. This study highlights two goals that can be achieved by incorporating high-frequency characterization into the reliability characteristics. The first one is assessing high-frequency performance throughout the device's lifetime to facilitate an accurate description of device/circuit functionality for high-frequency applications. Secondly, to explore the potential of high-frequency characterization as the means of scanning reliability effects within devices. S-parameters served as the high-frequency device's response and mapped onto a small-signal model to analyze different components of a fully depleted silicon-on-insulator MOSFET. The studied devices are subjected to two important DC stress patterns, i.e., Bias temperature instability stress and hot carrier stress. The hot carrier stress, which inherently suffers from the self-heating effect, resulted in the transistor's geometry-dependent magnitudes of hot carrier degradation. It is shown that the incorporation of the thermal resistance model is mandatory for the investigation of hot carrier degradation. The property of direct translation of small-signal parameter degradation to DC parameter degradation is used to develop a new S-parameter based bias temperature instability characterization methodology. The changes in gate-related small-signal capacitances after hot carrier stress reveals a distinct signature due to local change of flat-band voltage. The measured effects of gate-related small-signal capacitances post-stress are validated through transient physics-based simulations in Sentaurus TCAD.:Abstract Symbols Acronyms 1 Introduction 2 Fundamentals 2.1 MOSFETs Scaling Trends and Challenges 2.1.1 Silicon on Insulator Technology 2.1.2 FDSOI Technology 2.2 Reliability of Semiconductor Devices 2.3 RF Reliability 2.4 MOSFET Degradation Mechanisms 2.4.1 Hot Carrier Degradation 2.4.2 Bias Temperature Instability 2.5 Self-heating 3 RF Characterization of fully-depleted Silicon on Insulator devices 3.1 Scattering Parameters 3.2 S-parameters Measurement Flow 3.2.1 Calibration 3.2.2 De-embedding 3.3 Small-Signal Model 3.3.1 Model Parameters Extraction 3.3.2 Transistor Figures of Merit 3.4 Characterization Results 4 Self-heating assessment in Multi-finger Devices 4.1 Self-heating Characterization Methodology 4.1.1 Output Conductance Frequency dependence 4.1.2 Temperature dependence of Drain Current 4.2 Thermal Resistance Behavior 4.2.1 Thermal Resistance Scaling with number of fingers 4.2.2 Thermal Resistance Scaling with finger spacing 4.2.3 Thermal Resistance Scaling with GateWidth 4.2.4 Thermal Resistance Scaling with Gate length 4.3 Thermal Resistance Model 4.4 Design for Thermal Resistance Optimization 5 Bias Temperature Instability Investigation 5.1 Impact of Bias Temperature Instability stress on Device Metrics 5.1.1 Experimental Details 5.1.2 DC Parameters Drift 5.1.3 RF Small-Signal Parameters Drift 5.2 S-parameter based on-the-fly Bias Temperature Instability Characterization Method 5.2.1 Measurement Methodology 5.2.2 Results and Discussion 6 Investigation of Hot-carrier Degradation 6.1 Impact of Hot-carrier stress on Device performance 6.1.1 DC Metrics Degradation 6.1.2 Impact on small-signal Parameters 6.2 Implications of Self-heating on Hot-carrier Degradation in n-MOSFETs 6.2.1 Inclusion of Thermal resistance in Hot-carrier Degradation modeling 6.2.2 Convolution of Bias Temperature Instability component in Hot-carrier Degradation 6.2.3 Effect of Source and Drain Placement in Multi-finger Layout 6.3 Vth turn-around effect in p-MOSFET 7 Deconvolution of Hot-carrier Degradation and Bias Temperature Instability using Scattering parameters 7.1 Small-Signal Parameter Signatures for Hot-carrier Degradation and Bias Temperature Instability 7.2 TCAD Dynamic Simulation of Defects 7.2.1 Fixed Charges 7.2.2 Interface Traps near Gate 7.2.3 Interface Traps near Spacer Region 7.2.4 Combination of Traps 7.2.5 Drain Series Resistance effect 7.2.6 DVth Correction 7.3 Empirical Modeling based deconvolution of Hot-carrier Degradation 8 Conclusion and Recommendations 8.1 General Conclusions 8.2 Recommendations for Future Work A Directly measured S-parameters and extracted Y-parameters B Device Dimensions for Thermal Resistance Modeling C Frequency response of hot-carrier degradation (HCD) D Localization Effect of Interface Traps Bibliograph