Hybrid CMOS/memristor circuits

Abstract — This is a brief review of recent work on the prospective hybrid CMOS/memristor circuits. Such hybrids combine the flexibility, reliability and high functionality of the CMOS subsystem with very high density of nanoscale thin film resistance switching devices operating on different physical principles. Simulation and initial experimental results demonstrate that performance of CMOS/memristor circuits for several important applications is well beyond scaling limits of conventional VLSI paradigm. I

Redox-Active Molecules for Novel Nonvolatile Memory Applications

The continuous complementary metal‐oxide‐semiconductor (CMOS) scaling is reaching fundamental limits imposed by the heat dissipation and short‐channel effects, which will finally stop the increase of integration density and the MOSFET performance predicted by Moore’s law. Molecular technology has been aggressively pursued for decades due to its potential impact on future micro‐/nanoelectronics. Molecules, especially redox‐active molecules, have become attractive due to their intrinsic redox behavior, which provides an excellent basis for low‐power, high‐density, and high‐reliability nonvolatile memory applications. This chapter briefly reviews the development of molecular electronics in the application of nonvolatile memory. From the mechanical motion of molecules in the Langmuir‐Blodgett film to new families of redox‐active molecules, memory devices involving hybrid molecular technology have shown advantageous potential in fast speed, low‐power, and high‐density nonvolatile memory and will lead to promising on‐chip memory as well as future portable electronics applications

Integration of Ferroelectric HfO2 onto a III-V Nanowire Platform

The discovery of ferroelectricity in CMOS-compatible oxides, such as doped hafnium oxide, has opened new possibilities for electronics by reviving the use of ferroelectric implementations on modern technology platforms. This thesis presents the ground-up integration of ferroelectric HfO2 on a thermally sensitive III-V nanowire platform leading to the successful implementation of ferroelectric transistors (FeFETs), tunnel junctions (FTJs), and varactors for mm-wave applications. As ferroelectric HfO2 on III-V semiconductors is a nascent technology, a special emphasis is put on the fundamental integration issues and the various engineering challenges facing the technology.The fabrication of metal-oxide-semiconductor (MOS) capacitors is treated as well as the measurement methods developed to investigate the interfacial quality to the narrow bandgap III-V materials using both electrical and operando synchrotron light source techniques. After optimizing both the films and the top electrode, the gate stack is integrated onto vertical InAs nanowires on Si in order to successfully implement FeFETs. Their performance and reliability can be explained from the deeper physical understanding obtained from the capacitor structures.By introducing an InAs/(In)GaAsSb/GaSb heterostructure in the nanowire, a ferroelectric tunnel field effect transistor (ferro-TFET) is fabricated. Based on the ultra-short effective channel created by the band-to-band tunneling process, the localized potential variations induced by single ultra-scaled ferroelectric domains and individual defects are sensed and investigated. By intentionally introducing a gate-source overlap in the ferro-TFET, a non-volatile reconfigurable single-transistor solution for modulating an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing is implemented.Finally, by fabricating scaled ferroelectric MOS capacitors in the front-end with a dedicated and adopted RF and mm-wave backend-of-line (BEOL) implementation, the ferroelectric behavior is captured at RF and mm-wave frequencies

Reconfigurable Multifunctional van der Waals Ferroelectric Devices and Logic Circuits

In this work, we demonstrate the suitability of Reconfigurable Ferroelectric Field-Effect- Transistors (Re-FeFET) for designing non-volatile reconfigurable logic-in-memory circuits with multifunctional capabilities. Modulation of the energy landscape within a homojunction of a 2D tungsten diselenide (WSe$_2$) layer is achieved by independently controlling two split-gate electrodes made of a ferroelectric 2D copper indium thiophosphate (CuInP$_2$S$_6$) layer. Controlling the state encoded in the Program Gate enables switching between p, n and ambipolar FeFET operating modes. The transistors exhibit on-off ratios exceeding 10$^6$ and hysteresis windows of up to 10 V width. The homojunction can change from ohmic-like to diode behavior, with a large rectification ratio of 10$^4$. When programmed in the diode mode, the large built-in p-n junction electric field enables efficient separation of photogenerated carriers, making the device attractive for energy harvesting applications. The implementation of the Re-FeFET for reconfigurable logic functions shows how a circuit can be reconfigured to emulate either polymorphic ferroelectric NAND/AND logic-in-memory or electronic XNOR logic with long retention time exceeding 10$^4$ seconds. We also illustrate how a circuit design made of just two Re-FeFETs exhibits high logic expressivity with reconfigurability at runtime to implement several key non-volatile 2-input logic functions. Moreover, the Re-FeFET circuit demonstrates remarkable compactness, with an up to 80% reduction in transistor count compared to standard CMOS design. The 2D van de Waals Re-FeFET devices therefore exhibit groundbreaking potential for both More-than-Moore and beyond-Moore future of electronics, in particular for an energy-efficient implementation of in-memory computing and machine learning hardware, due to their multifunctionality and design compactness.Comment: 23 pages, 5 figures; Supporting Information: 12 pages, 6 figure

Planar Electrostatically Doped Reconfigurable Schottky Barrier FDSOI Field-Effect Transistor Structures

In the last 50 years, our economy and society have obviously been influenced and shaped to a great extent by electronic devices. This substantial impact of electronics is the result of a continuous performance improvement based on the scaling, i.e. shrinking, of MOSFET devices in complementary integrated circuits, following Moore's law. As the MOSFET feature sizes are approaching atomistic dimensions, the scaling trend slowed down considerably and is even threatened for sub-10 nm technology nodes. Further, additional advancements are increasingly difficult to realize both from the technological and especially the economical perspective. Therefore, technologies that have the potential to supersede the CMOS technology in the future are the topic of intensive investigation by both researchers and the industry. An attractive solution is the leveraging of existing semiconductor technologies based on emerging research devices (ERD) offering novel characteristics, which enable new circuit architectures in future nanoscale logic circuits. A possible ERD contender are polarity controllable or reconfigurable MOSFET (RFET) concepts. Generally, RFET devices are able to switch between n- and p-type conduction by the application of an electrical signal. Therefore, RFET promise increased complex systems with a lower device count decreasing the costs per basic logic function based on their higher logic expressiveness. The focus of this work lies in the successful transfer of a predecessor silicon nanowire (NW) RFET technology into a planar RFET device, while simultaneously optimizing the resulting RFET for reconfigurable as well as conventional CMOS circuits. As for the predecessor NW RFET, the planar approach features a doping-less CMOS compatible fabrication process on a conventional SOI substrate and obtains its reconfigurability by electrostatic doping. The device can be regarded as a entanglement of two MOSFET in one structure, i.e. a depletion mode FET centered on top of a backside enhancement mode Schottky barrier FET (SBFET). The backside SBFET establishes the conductive channel consisting of the desired charge carrier type via an appropriate potential on its gate electrode. The topside FET controls the charge carrier flow between source and drain by locally depleting this channel given an opposite potential on its gate electrode with respect to the backside gate electrode. Two generations of devices have been successfully processed, while different gate electrode materials, i.e. nickel, aluminum and reactively sputtered tungsten-titanium-nitride, have been introduced to the device structure. As n- and p-type symmetry of the very same device is essential for RFET circuit design, tungsten-titanium-nitride is experimentally identified as a possible mid-gap metal gate electrode for RFET devices. Also, a Schottky barrier adjustment process for ideal n- and p-type symmetry based on silicide induced dopant segregation is experimentally demonstrated. Extensive electrical characterizations supported by calibrated TCAD simulations are presented, demonstrating experimental sub-threshold slopes of 65 mV/dec and on-to-off current ratios of over 9 decades. Based on TCAD simulations and supported by experimental results, the design space of the device concept is explored in order to gather predictive results for future scaled device optimization. Further, the high temperature (HT) performance is evaluated and compared to the predecessor NW RFET devices as well as to a state-of-the-art industrial high reliability HT MOSFET clearly illustrating the on par performance of the planar RFET concept with respect to off-state leakage current

프로그램 가능한 하부 전극 어레이 구조를 갖는 고효율 재구성 가능 소자

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 이종호.본 논문에서는 비 휘발성 메모리 (NVM) 기능을 갖는 프로그램 가능한 하부 전극 어레이 (Bottom gate array) 로 구성된 새로운 폴리 실리콘 재구성 가능 소자를 최초로 고안하고 제작 및 분석하였다. 제안된 소자는 소자의 크기, 신뢰성, 균일성 및 재현성 측면에서 매우 효율적이다. 하부 전극 어레이에 직접 바이어스를 인가하거나, 또는 하부 전극의 프로그램/이레이즈 상태를 변화 시킴으로써, 제안된 재구성가능 소자는 n-/p-MOSFET, n-p/p-n 다이오드 중 하나의 형태로 동작할 수 있다. 또한, 소자의 MOSFET 동작에서, 문턱 전압 (Vth)과 접합 저항 (RC)은 하부 전극에 의해 독립적으로 제어 가능하며 이는 제안된 재구성 가능 소자의 고유한 장점이다. 제작된 소자는 n-/p-MOSFET 동작에서 기존의 폴리 실리콘 채널 기반 소자들과 유사한 약 120mV/dec 의 역치하 기울기 (subthreshold swing, SS) 및 106 이상의 on/off 전류 비 특성을 갖는다. 두 개의 동일한 재구성 가능 소자를 이용하여 제작된 풀 스윙 CMOS 인버터 로직 게이트의 동작도 성공적으로 구현되었다. 제작된 소자의 DC I-V 특성, 드레인 전류의 온도 의존성 및 저주파 잡음 특성 측정을 통하여, 하부 전극 전압과 채널 저항 및 쇼트키 접합 저항의 관계를 연구하였다. 이를 통하여 알루미늄 소스/드레인은 n 혹은 p 형으로 전기적으로 도핑된 폴리 실리콘 채널과 쇼트키 접합을 형성하게 되고, 소자의 전류는 쇼트키 역방향 접합 터널링에 의하여 결정됨을 확인하였다. 제작된 소자에 대한 분석을 바탕으로 소자의 제작 공정 최적화를 진행하였으며, 제작 공정 최적화를 통하여 개선된 균일성과 평탄도를 갖는 안정된 하부 전극 구조를 구현하였고 이를 통해 개선된 프로그램/이레이즈 성능과 온 커런트의 증가를 확인하였다. 최적화된 소자의 역치하 기울기는 이중 게이트 동작에서 약 90 mV/dec 로 게이트 제어력이 향상되었고, on/off 전류비는 107 이상으로 증가하였다. 공정 최적화를 통해 각각의 소자를 완전히 격리 시킴으로써, 네 개의 동일한 재구성 가능 소자를 이용하여 제작된 NAND/NOR 로직 게이트의 동작 또한 성공적으로 구현하였다. 또한, 실험과 시뮬레이션을 통하여 소스/드레인 메탈의 종류와 게이트 스택의 전기적 두께가 소자의 특성에 미치는 영향에 대해서도 분석 하였다.A novel poly-Si reconfigurable device with programmable bottom gate array having non-volatile memory (NVM) functionality was demonstrated for the first time. The device is very efficient in terms of device size, reliability, uniformity, and reproducibility. By changing bias or program/erase state (PGM/ERS) of the bottom gates (BGs), a device can be transformed to behave one of the following devices: n-/p-MOSFET, n-p, and p-n diode. Threshold voltage (Vth) and contact resistance (Rc) of MOSFETs can be controlled independently by the BGs. The subthreshold swing (SS) and Ion/Ioff of the n-/p-MOSFETs are ~120 mV/dec and >106, respectively, which are comparable to those of conventional poly-Si devices. Full-swing CMOS inverter logic gates implemented by using two identical reconfigurable devices were successfully demonstrated. Relationship between bottom gate biases and resistance of channel and Schottky junction was investigated by DC I-V, temperature dependency of ID, and low frequency noise measurement. Aluminum source/drain (S/D) layer forms Schottky junction with poly-Si body being electrically doped with n- or p-type, and the current mechanism is dominated by Schottky reverse junction tunneling. Optimization of fabrication process was performed and stable BG structure with enhanced uniformity and flatness was achieved. The optimized device demonstrated enhanced PGM/ERS performance and improved on-current characteristics. Gate controllability was also enhanced in the double gate operation with SS of ~90 mV/dec, and Ion/Ioff increased to more than 107. A full-swing CMOS inverter and NAND/NOR logic gates implemented by using four identical reconfigurable devices were also successfully demonstrated with complete device isolation by process optimization. The effect of S/D metal and electrical oxide thickness (EOT) of the gate stack on the device characteristics were investigated by both experiments and simulations.Chapter 1.Introduction 1 1.1 Motivation 1 1.2 Background of Reconfigurable Devices 9 1.3 Thesis Organization 16 Chapter 2.Proposed Reconfigurable Device 18 2.1 Structure and Features of Proposed Reconfigurable Device 18 2.2 Fundamentals of Proposed Reconfigurable Device 24 Chapter 3.Fabrication of Proposed Reconfigurable Device 30 3.1 Mask Layout and Fabrication Issues 30 3.2 Bottom Gate Formation 38 3.2.1 Nitride Spacer Method. 38 3.2.2 Poly-Si CMP Method 42 3.3 Overall Fabrication Process 47 Chapter 4.Characterization of Proposed Reconfigurable Device 55 4.1 I-V Characteristics of n- and p-MOSFETs 55 4.2 MOSFET I-V with PGM/ERS State of Bottom Gates 61 4.3 p-n / n-p diode operations 67 4.4 Logic Gate Operations 72 Chapter 5.Analysis of Schottky Contact Resistance 75 5.1 Schottky barrier modulation by bottom gate bias 75 5.2 Temperature Dependence of Reconfigurable Device 81 5.3 Noise characteristics of MOSFET with bottom gate biases 84 Chapter 6.Process Optimization and On-current Improvement 87 6.1 Performance of Proposed Device 87 6.2 Process Optimization 89 6.2.1 SiO2 fin Method 89 6.2.2 Enhanced I-V characteristics 96 6.3 On-current Improvement 102 Chapter 7.Conclusions 105 Bibliography 108 Abstract in Korean 116Docto

Crosstalk computing: circuit techniques, implementation and potential applications

Title from PDF of title [age viewed January 32, 2022Dissertation advisor: Mostafizur RahmanVitaIncludes bibliographical references (page 117-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2020This work presents a radically new computing concept for digital Integrated Circuits (ICs), called Crosstalk Computing. The conventional CMOS scaling trend is facing device scaling limitations and interconnect bottleneck. The other primary concern of miniaturization of ICs is the signal-integrity issue due to Crosstalk, which is the unwanted interference of signals between neighboring metal lines. The Crosstalk is becoming inexorable with advancing technology nodes. Traditional computing circuits always tries to reduce this Crosstalk by applying various circuit and layout techniques. In contrast, this research develops novel circuit techniques that can leverage this detrimental effect and convert it astutely to a useful feature. The Crosstalk is engineered into a logic computation principle by leveraging deterministic signal interference for innovative circuit implementation. This research work presents a comprehensive circuit framework for Crosstalk Computing and derives all the key circuit elements that can enable this computing model. Along with regular digital logic circuits, it also presents a novel Polymorphic circuit approach unique to Crosstalk Computing. In Polymorphic circuits, the functionality of a circuit can be altered using a control variable. Owing to the multi-functional embodiment in polymorphic-circuits, they find many useful applications such as reconfigurable system design, resource sharing, hardware security, and fault-tolerant circuit design, etc. This dissertation shows a comprehensive list of polymorphic logic gate implementations, which were not reported previously in any other work. It also performs a comparison study between Crosstalk polymorphic circuits and existing polymorphic approaches, which are either inefficient due to custom non-linear circuit styles or propose exotic devices. The ability to design a wide range of polymorphic logic circuits (basic and complex logics) compact in design and minimal in transistor count is unique to Crosstalk Computing, which leads to benefits in the circuit density, power, and performance. The circuit simulation and characterization results show a 6x improvement in transistor count, 2x improvement in switching energy, and 1.5x improvement in performance compared to counterpart implementation in CMOS circuit style. Nevertheless, the Crosstalk circuits also face issues while cascading the circuits; this research analyzes all the problems and develops auxiliary circuit techniques to fix the problems. Moreover, it shows a module-level cascaded polymorphic circuit example, which also employs the auxiliary circuit techniques developed. For the very first time, it implements a proof-of-concept prototype Chip for Crosstalk Computing at TSMC 65nm technology and demonstrates experimental evidence for runtime reconfiguration of the polymorphic circuit. The dissertation also explores the application potentials for Crosstalk Computing circuits. Finally, the future work section discusses the Electronic Design Automation (EDA) challenges and proposes an appropriate design flow; besides, it also discusses ideas for the efficient implementation of Crosstalk Computing structures. Thus, further research and development to realize efficient Crosstalk Computing structures can leverage the comprehensive circuit framework developed in this research and offer transformative benefits for the semiconductor industry.Introduction and Motivation -- More Moore and Relevant Beyond CMOS Research Directions -- Crosstalk Computing -- Crosstalk Circuits Based on Perception Model -- Crosstalk Circuit Types -- Cascading Circuit Issues and Sollutions -- Existing Polymorphic Circuit Approaches -- Crosstalk Polymorphic Circuits -- Comparison and Benchmarking of Crosstalk Gates -- Practical Realization of Crosstalk Gates -- Poential Applications -- Conclusion and Future Wor