FPGA implementation of real-time human motion recognition on a reconfigurable video processing architecture

In recent years, automatic human motion recognition has been widely researched within the computer vision and image processing communities. Here we propose a real-time embedded vision solution for human motion recognition implemented on a ubiquitous device. There are three main contributions in this paper. Firstly, we have developed a fast human motion recognition system with simple motion features and a linear Support Vector Machine(SVM) classifier. The method has been tested on a large, public human action dataset and achieved competitive performance for the temporal template (eg. ``motion history image") class of approaches. Secondly, we have developed a reconfigurable, FPGA based video processing architecture. One advantage of this architecture is that the system processing performance can be reconfigured for a particular application, with the addition of new or replicated processing cores. Finally, we have successfully implemented a human motion recognition system on this reconfigurable architecture. With a small number of human actions (hand gestures), this stand-alone system is performing reliably, with an 80% average recognition rate using limited training data. This type of system has applications in security systems, man-machine communications and intelligent environments

Real-time human action recognition on an embedded, reconfigurable video processing architecture

Copyright @ 2008 Springer-Verlag.In recent years, automatic human motion recognition has been widely researched within the computer vision and image processing communities. Here we propose a real-time embedded vision solution for human motion recognition implemented on a ubiquitous device. There are three main contributions in this paper. Firstly, we have developed a fast human motion recognition system with simple motion features and a linear Support Vector Machine (SVM) classifier. The method has been tested on a large, public human action dataset and achieved competitive performance for the temporal template (eg. “motion history image”) class of approaches. Secondly, we have developed a reconfigurable, FPGA based video processing architecture. One advantage of this architecture is that the system processing performance can be reconfiured for a particular application, with the addition of new or replicated processing cores. Finally, we have successfully implemented a human motion recognition system on this reconfigurable architecture. With a small number of human actions (hand gestures), this stand-alone system is performing reliably, with an 80% average recognition rate using limited training data. This type of system has applications in security systems, man-machine communications and intelligent environments.DTI and Broadcom Ltd

A New Development Framework for Multi-Core Processor based Smart-Camera Implementations

International audienceThe exponential evolution of the smart camera processing performances is directly linked to the improvements on hardware processing elements. Nowadays, high processing performances can be reached considering hardware targets which enables a high level of task parallelism to be implemented. Highly regular tasks are good candidate for a reconfigurable logic implementation and less regular parts of the algorithm could be described on the processor. Meanwhile the prototyping time is related to the selected target and the associated development methodology. The implementation on reconfigurable logic is highly efficient in exploiting the intrinsic task parallelism nevertheless can be time consuming using traditional methodology (i.e. Hardware Language Description). Several approaches can be considered to decrease the proto-typing time and to conserve high processing performances for instance implementation based on: • heterogeneous architectures [1] that mixed reconfig-urable logic (i.e. FPGA) and embedded processor, • high-level abstraction description and the associated fast prototyping tools [2][3][4], • multi-core processor architectures such as Digital Signal Processors (DSP), Graphic Processor Units (GPU) or even Generic Purpose Processor (GPP). In this paper, we propose to focus on implementation based on GPP due to the emergence of new generation of low-cost multi-core processors which enables high processing performances to be reached and therefore to match with some constraints of complex image-processing algorithms. The key idea of this development is to be able to propose fast prototyping using a low-cost smart camera based on this kind of target. Hence, we have developed a new framework dedicated to multi-core processor associated with an image sensor. The framework aims to offer a high degree of flexibility for managing the tasks and the memory allocation. Hence, the framework enables the priority and the allocation of each task to be controlled. Each task (or binary) is independent in terms of execution nevertheless it can be linked and controlled using a higher hierarchy level binary. The image acquisition task can be completely independent from the other processing tasks. One processor's core can even be dedicated to the acquisition task to guarantee a constant input data-flow to the image processing tasks. The data exchange is defined in POSIX, each binary can be therefore coded differently (for instance in C or C++, or in another languages) and offer a relative Operating System (OS) compatibility. The memory management enables a sequence of images to be automatically stored and a simultaneous access to be granted for several processings. The framework includes an interface dedicated to the management of the tasks: the user can add or suppress a binary during the runtime, logs or processing results can be visualised for each task

Digital implementation of the cellular sensor-computers

Two different kinds of cellular sensor-processor architectures are used nowadays in various applications. The first is the traditional sensor-processor architecture, where the sensor and the processor arrays are mapped into each other. The second is the foveal architecture, in which a small active fovea is navigating in a large sensor array. This second architecture is introduced and compared here. Both of these architectures can be implemented with analog and digital processor arrays. The efficiency of the different implementation types, depending on the used CMOS technology, is analyzed. It turned out, that the finer the technology is, the better to use digital implementation rather than analog