Software Defined Radio Solutions for Wireless Communications Systems

Wireless technologies have been advancing rapidly, especially in the recent years. Design, implementation, and manufacturing of devices supporting the continuously evolving technologies require great efforts. Thus, building platforms compatible with different generations of standards and technologies has gained a lot of interest. As a result, software defined radios (SDRs) are investigated to offer more flexibility and scalability, and reduce the design efforts, compared to the conventional fixed-function hardware-based solutions.This thesis mainly addresses the challenges related to SDR-based implementation of today’s wireless devices. One of the main targets of most of the wireless standards has been to improve the achievable data rates, which imposes strict requirements on the processing platforms. Realizing real-time processing of high throughput signal processing algorithms using SDR-based platforms while maintaining energy consumption close to conventional approaches is a challenging topic that is addressed in this thesis.Firstly, this thesis concentrates on the challenges of a real-time software-based implementation for the very high throughput (VHT) Institute of Electrical and Electronics Engineers (IEEE) 802.11ac amendment from the wireless local area networks (WLAN) family, where an SDR-based solution is introduced for the frequency-domain baseband processing of a multiple-input multipleoutput (MIMO) transmitter and receiver. The feasibility of the implementation is evaluated with respect to the number of clock cycles and the consumed power. Furthermore, a digital front-end (DFE) concept is developed for the IEEE 802.11ac receiver, where the 80 MHz waveform is divided to two 40 MHz signals. This is carried out through time-domain digital filtering and decimation, which is challenging due to the latency and cyclic prefix (CP) budget of the receiver. Different multi-rate channelization architectures are developed, and the software implementation is presented and evaluated in terms of execution time, number of clock cycles, power, and energy consumption on different multi-core platforms.Secondly, this thesis addresses selected advanced techniques developed to realize inband fullduplex (IBFD) systems, which aim at improving spectral efficiency in today’s congested radio spectrum. IBFD refers to concurrent transmission and reception on the same frequency band, where the main challenge to combat is the strong self-interference (SI). In this thesis, an SDRbased solution is introduced, which is capable of real-time mitigation of the SI signal. The implementation results show possibility of achieving real-time sufficient SI suppression under time-varying environments using low-power, mobile-scale multi-core processing platforms. To investigate the challenges associated with SDR implementations for mobile-scale devices with limited processing and power resources, processing platforms suitable for hand-held devices are selected in this thesis work. On the baseband processing side, a very long instruction word (VLIW) processor, optimized for wireless communication applications, is utilized. Furthermore, in the solutions presented for the DFE processing and the digital SI canceller, commercial off-the-shelf (COTS) multi-core central processing units (CPUs) and graphics processing units (GPUs) are used with the aim of investigating the performance enhancement achieved by utilizing parallel processing.Overall, this thesis provides solutions to the challenges of low-power, and real-time software-based implementation of computationally intensive signal processing algorithms for the current and future communications systems

Design and implementation of an ETSI-SDR OFDM transmitter with power amplifier linearizer

Satellite radio has attained great popularity because of its wide range of geographical coverage and high signal quality as compared to the terrestrial broadcasts. Most Satellite Digital Radio (SDR) based systems favor multi-carrier transmission schemes, especially, orthogonal frequency division multiplexing (OFDM) transmission because of high data transfer rate and spectral efficiency. It is a challenging task to find a suitable platform that supports fast data rates and superior processing capabilities required for the development and deployment of the new SDR standards. Field programmable gate array (FPGA) devices have the potential to become suitable development platform for such standards. Another challenging factor in SDR systems is the distortion of variable envelope signals used in OFDM transmission by the nonlinear RF power amplifiers (PA) used in the base station transmitters. An attractive option is to use a linearizer that would compensate for the nonlinear effects of the PA. In this research, an OFDM transmitter, according to European Telecommunications Standard Institute (ETSI) SDR Technical Specifications 2007-2008, was designed and implemented on a low-cost Xilinx FPGA platform. A weakly nonlinear PA, operating in the L-band SDR frequency (1.450-1.490GHz), was used for signal transmission. An FPGA-based, low-cost, adaptive linearizer was designed and implemented based on the digital predistortion (DPD) reference design from Xilinx, to correct the distortion effects of the PA on the transmitted signal

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

A Novel Long-Range Passive UHF RFID System over Twisted-pair Cable

Radio Frequency Identification (RFID) is one of the most representative, rapidly growing, and highly extendable technologies, which uses electromagnetic waves in accordance with specific communications standards and regulations to identify, track, or even localise desired objects. However, due to its high cost, limited read range, and uncertain reliability, its adoption still lags, especially in large-scale organisations. Even though an RFID distributed antenna system (DAS) can greatly improve the detection range and read rate of a single reader when system uses different combinations of antenna states with frequency and phase hopping, the lossy and heavy coaxial cables between reader and antennas still limits the system coverage and design flexibility for wide-area passive UHF RFID applications. In order to develop a cost-efficient and flexibly-installed passive RFID DAS, a novel large-range passive UHF RFID system over twisted-pair cable is proposed in this dissertation. This new system consists of one baseband central controller and one antenna subsystem, connected by a commonly used twisted-pair cable. It is shown that transmitting/receiving low frequency baseband signals over a twisted-pair cable can significantly reduce cable attenuation and extend the communication distance. A simulation is conducted to demonstrate that frequency and phase hopping can also be remotely controlled to fit this system structure by slightly varying the frequency or phase of the input reference signal of the frequency synthesis system. The features of twisted-pair cable in terms of its low cost, light weight, and bend radius greatly improve the design and installation flexibility of an RFID system. The implemented system is designed based on the ISO 18000-6C and EPC Class 1 Generation 2 standards, and can operate according to FCC (902-928 MHz) and ETSI (865-868MHz) regulations. The results of the measurement show the reader can achieve a sensitivity of - 94.5 dBm over 30 m Cat5e cable, and its sensitivity can still remain at around -94.2 dBm over 150 m Cat5e cable. The experimental results of tag detection show that the passive tags can be successfully detected over a 6 m wireless range following a 300 m of twisted-pair cable between the central controller and antenna. This detection range cannot be achieved by existing commercial RFID systems. Since the transmission and reception in a RFID system are simultaneous, finite isolation of the circulator/directional coupler and environmentally dependent reflection ratio of the antenna lead to serious leakage problems. Leakage can directly cause sensitivity degradation due to saturation of the RF components. A fast leakage suppression block is developed in efforts to solve this problem. Measurements show that this new canceller can deliver an average suppression of 36.9 dB, and this excellent performance remains when the system uses frequency hopping. With help of an improved scanning algorithm, this canceller can find its optimal status within 38 ms, and this settling time is short enough for most commercial RFID readers. By reducing the number of voltage samples taken, the convergence time can be further improved. To fully investigate this new passive UHF RFID system value, a comparison study between the new system and a commercial system is conducted. This new automatic passive UHF RFID system is confirmed to deliver high performance long-range passive tag detection. Particular advantages are shown in the fast tag read rate and capability of uplink SNR improvement. This novel system is also superior to conventional RFID systems in terms of link distance, link cost, and installation flexibility

Modeling and Digital Mitigation of Transmitter Imperfections in Radio Communication Systems

To satisfy the continuously growing demands for higher data rates, modern radio communication systems employ larger bandwidths and more complex waveforms. Furthermore, radio devices are expected to support a rich mixture of standards such as cellular networks, wireless local-area networks, wireless personal area networks, positioning and navigation systems, etc. In general, a "smart'' device should be flexible to support all these requirements while being portable, cheap, and energy efficient. These seemingly conflicting expectations impose stringent radio frequency (RF) design challenges which, in turn, call for their proper understanding as well as developing cost-effective solutions to address them. The direct-conversion transceiver architecture is an appealing analog front-end for flexible and multi-standard radio systems. However, it is sensitive to various circuit impairments, and modern communication systems based on multi-carrier waveforms such as Orthogonal Frequency Division Multiplexing (OFDM) and Orthogonal Frequency Division Multiple Access (OFDMA) are particularly vulnerable to RF front-end non-idealities.This thesis addresses the modeling and digital mitigation of selected transmitter (TX) RF impairments in radio communication devices. The contributions can be divided into two areas. First, new modeling and digital mitigation techniques are proposed for two essential front-end impairments in direct-conversion architecture-based OFDM and OFDMA systems, namely inphase and quadrature phase (I/Q) imbalance and carrier frequency offset (CFO). Both joint and de-coupled estimation and compensation schemes for frequency-selective TX I/Q imbalance and channel distortions are proposed for OFDM systems, to be adopted on the receiver side. Then, in the context of uplink OFDMA and Single Carrier FDMA (SC-FDMA), which are the air interface technologies of the 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) and LTE-Advanced systems, joint estimation and equalization techniques of RF impairments and channel distortions are proposed. Here, the challenging multi-user uplink scenario with unequal received power levels is investigated where I/Q imbalance causes inter-user interference. A joint mirror subcarrier processing-based minimum mean-square error (MMSE) equalizer with an arbitrary number of receiver antennas is formulated to effectively handle the mirror sub-band users of different power levels. Furthermore, the joint channel and impairments filter responses are efficiently approximated with polynomial-based basis function models, and the parameters of basis functions are estimated with the reference signals conforming to the LTE uplink sub-frame structure. The resulting receiver concept adopting the proposed techniques enables improved link performance without modifying the design of RF transceivers.Second, digital baseband mitigation solutions are developed for the TX leakage signal-induced self-interference in frequency division duplex (FDD) transceivers. In FDD transceivers, a duplexer is used to connect the TX and receiver (RX) chains to a common antenna while also providing isolation to the receiver chain against the powerful transmit signal. In general, the continuous miniaturization of hardware and adoption of larger bandwidths through carrier aggregation type noncontiguous allocations complicates achieving sufficient TX-RX isolation. Here, two different effects of the transmitter leakage signal are investigated. The first is TX out-of-band (OOB) emissions and TX spurious emissions at own receiver band, due to the transmitter nonlinearity, and the second is nonlinearity of down-converter in the RX that generates second-order intermodulation distortion (IMD2) due to the TX in-band leakage signal. This work shows that the transmitter leakage signal-induced interference depends on an equivalent leakage channel that models the TX path non-idealities, duplexer filter responses, and the RX path non-idealities. The work proposes algorithms that operate in the digital baseband of the transceiver to estimate the TX-RX non-idealities and the duplexer filter responses, and subsequently regenerating and canceling the self-interference, thereby potentially relaxing the TX-RX isolation requirements as well as increasing the transceiver flexibility.Overall, this thesis provides useful signal models to understand the implications of different RF non-idealities and proposes compensation solutions to cope with certain RF impairments. This is complemented with extensive computer simulations and practical RF measurements to validate their application in real-world radio transceivers

Real-Time Narrowband and Wideband Beamforming Techniques for Fully-Digital RF Arrays

Elemental digital beamforming offers increased flexibility for multi-function radio frequency (RF) systems supporting radar and communications applications. As fully digital arrays, components, and subsystems are becoming more affordable in the military and commercial industries, analog components such as phase shifters, filters, and mixers have begun to be replaced by digital circuits which presents efficiency challenges in power constrained scenarios. Furthermore, multi-function radar and communications systems are exploiting the multiple simultaneous beam capability provided by digital at every element beamforming. Along with further increasing data samples rates and increasing instantaneous bandwidths (IBW), real time processing in the digital domain has become a challenge due to the amount of data produced and processed in current systems. These arrays generate hundreds of gigabits per second of data throughput or more which is costly to send off-chip to an adjunct processor fundamentally limiting the overall performance of an RF array system. In this dissertation, digital filtering techniques and architectures are described which calibrate and beamform both narrowband and wideband RF arrays on receive. The techniques are shown to optimize one or many parameters of the digital transceiver system to improve the overall system efficiency. Digitally beamforming in the beamspace is shown to further increase the processing efficiency of an adaptive system compared to state of the art frequency domain approaches by minimizing major processing bottlenecks of generating adaptive filter coefficients. The techniques discussed are compared and contrasted across different hardware processor modules including field-programmable gate arrays (FPGAs), graphical processing units (GPUs), and central processing units (CPUs)

Space time transceiver design over multipath fading channels

Imperial Users onl