A Micro Power Hardware Fabric for Embedded Computing

Field Programmable Gate Arrays (FPGAs) mitigate many of the problemsencountered with the development of ASICs by offering flexibility, faster time-to-market, and amortized NRE costs, among other benefits. While FPGAs are increasingly being used for complex computational applications such as signal and image processing, networking, and cryptology, they are far from ideal for these tasks due to relatively high power consumption and silicon usage overheads compared to direct ASIC implementation. A reconfigurable device that exhibits ASIC-like power characteristics and FPGA-like costs and tool support is desirable to fill this void. In this research, a parameterized, reconfigurable fabric model named as domain specific fabric (DSF) is developed that exhibits ASIC-like power characteristics for Digital Signal Processing (DSP) style applications. Using this model, the impact of varying different design parameters on power and performance has been studied. Different optimization techniques like local search and simulated annealing are used to determine the appropriate interconnect for a specific set of applications. A design space exploration tool has been developed to automate and generate a tailored architectural instance of the fabric.The fabric has been synthesized on 160 nm cell-based ASIC fabrication process from OKI and 130 nm from IBM. A detailed power-performance analysis has been completed using signal and image processing benchmarks from the MediaBench benchmark suite and elsewhere with comparisons to other hardware and software implementations. The optimized fabric implemented using the 130 nm process yields energy within 3X of a direct ASIC implementation, 330X better than a Virtex-II Pro FPGA and 2016X better than an Intel XScale processor

Directions in propulsion control

Discussed here is research at NASA Lewis in the area of propulsion controls as driven by trends in advanced aircraft. The objective of the Lewis program is to develop the technology for advanced reliable propulsion control systems and to integrate the propulsion control with the flight control for optimal full-system control

Toward Programmable Microwave Photonics Processors

[EN] We describe the advances that we, and others, have reported during the last years in the area of programmable microwave photonic processors. Following a brief historical sketch, we provide a detailed account of the salient theoretical and experimental results recently reported on waveguide mesh optical core processors. The incorporation of a waveguide mesh optical core into the general microwave photonics programmable processor architecture is then addressed. We illustrate through different examples how this processor can be programmed to enable the most important functionalities required in microwave photonics.This work was supported in part by the European research Council under Grant ERC-ADG-2016-471715 UMWP-CHIP and in part by the Generalitat Valencia under Project PROMETEO-2017-103.Pérez-López, D.; Gasulla Mestre, I.; Capmany Francoy, J. (2018). Toward Programmable Microwave Photonics Processors. Journal of Lightwave Technology. 36(2):519-532. https://doi.org/10.1109/JLT.2017.2778741S51953236

A programmable, multi-format photonic transceiver platform enabling flexible optical networks

Development of programmable photonic devices for future flexible optical networks is ongoing. To this end, an innovative, multi-format QAM transmitter design is presented. It comprises a segmented-electrode InP IQ-MZM to be fabricated in InP, which can be directly driven by low-power CMOS logic. Arbitrary optical QAM format generation is made possible using only binary electrical signals, without the need for high-performance DACs and high-swing linear drivers. The concept enables a host of Tx-side DSP functionality, including the spectral shaping needed for Nyquist-WDM system concepts. In addition, we report on the development of an optical channel MUX/DEMUX, based on arrays of microresonator filters with reconfigurable bandwidths and center wavelengths. The device is intended for operation with multi-format flexible transceivers, enabling Dense (D)WDM superchannel aggregation and arbitrary spectral slicing in the context of a flexible grid environment

Reconfigurable network systems and software-defined networking

Modern high-speed networks have evolved from relatively static networks to highly adaptive networks facilitating dynamic reconfiguration. This evolution has influenced all levels of network design and management, introducing increased programmability and configuration flexibility. This influence has extended from the lowest level of physical hardware interfaces to the highest level of network management by software. A key representative of this evolution is the emergence of softwaredefined networking (SDN). In this paper, we review the current state of the art in reconfigurable network systems, covering hardware reconfiguration, SDN, and the interplay between them. We take a top-down approach, starting with a tutorial on software-defined networks. We then continue to discuss programming languages as the linking element between different levels of software and hardware in the network. We review electronic switching systems, highlighting programmability and reconfiguration aspects, and describe the trends in reconfigurable network elements. Finally, we describe the state of the art in the integration of photonic transceiver and switching elements with electronic technologies, and consider the implications for SDN and reconfigurable network systems.This work was jointly supported by the UKs Engineering and Physical Sciences Research Council (EPSRC) Internet Project EP/H040536/1, an EPSRC Research Fellowship grant to Philip Watts (EP/I004157/2), and DARPA and AFRL under contract FA8750-11-C-0249.This is the final version of the article. It first appeared from IEEE via http://dx.doi.org/10.1109/JPROC.2015.243573