On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce tolerance against possible faults in an integrated circuit. This thesis studies and presents fault tolerance methods for network-onchip (NoC) which is a design paradigm targeted for very large systems-onchip. In a NoC resources, such as processors and memories, are connected to a communication network; comparable to the Internet. Fault tolerance in such a system can be achieved at many abstraction levels. The thesis studies the origin of faults in modern technologies and explains the classification to transient, intermittent and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Networks-on-chip are approached by exploring their main design choices: the selection of a topology, routing protocol, and flow control method. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model. The data link layer provides a reliable communication link over a physical channel. Error control coding is an efficient fault tolerance method especially against transient faults at this abstraction level. Error control coding methods suitable for on-chip communication are studied and their implementations presented. Error control coding loses its effectiveness in the presence of intermittent and permanent faults. Therefore, other solutions against them are presented. The introduction of spare wires and split transmissions are shown to provide good tolerance against intermittent and permanent errors and their combination to error control coding is illustrated. At the network layer positioned above the data link layer, fault tolerance can be achieved with the design of fault tolerant network topologies and routing algorithms. Both of these approaches are presented in the thesis together with realizations in the both categories. The thesis concludes that an optimal fault tolerance solution contains carefully co-designed elements from different abstraction levelsSiirretty Doriast

Analysis and Simulation of the Signals Transmission in the DVB-H/SH Standards

Tato disertační práce se zabývá analýzou, simulací a měřením zpracování a přenosu signálů digitální televize pro příjem mobilního TV vysílání ve standardech DVB-H a DVB-SH. Tyto standardy vycházejí z předpokladu, že příjem signálu je charakterizován modely přenosových kanálů s vícecestným šířením. Tyto, tzv. únikové kanály, jsou charakterizovány hlavně zpožděním a ziskem jednotlivých cest. V závislosti na dalších parametrech (rychlost přijímače, Dopplerovské spektrum), je možné rozdělit únikové kanály do třech hlavních skupin: mobilní, přenosné a fixní. Dá se předpokládat, že v různých modelech kanálů bude přenášený signál různě ovlivněn. Proto je potřebné najít optimální parametry systémů (DVB-H/SH) pro kvalitní příjem vysílaných služeb mobilní televize, což je hlavním cílem této disertační práci. Pro tento účel byly vytvořeny dvě vhodné aplikace (jedna pro DVB-H a jedna pro DVB-SH) s GUI v prostředí MATLAB, které umožňují simulovat a analyzovat míru zkreslení signálu v případě mobilních, přenosných a fixních scénářů přenosu. Navíc, tyto aplikace obsahují i druhý samostatný simulátor pro nastavení a modifikaci parametrů jednotlivých přenosových cest. Díky tomu je možné zhodnotit vliv parametrů celého systému a kanálových modelů na dosaženou chybovost (BER a MER) a kvalitu přenosu. Ve všech přenosových scénářích (v závislosti na poměru C/N) byly získané, vyhodnocené a diskutované zkreslení signálů. Navíc, u standardu DVB-H, všechny získané výsledky ze simulací byly ověřeny měřením. Rozdíly mezi dosaženými výsledky (simulace a měření) byly rovněž podrobeny diskuzi. Tuto disertační práci je možné rozdělit do čtyř hlavních částí. První část disertační práce se zabývá rešerší současného vývoje v oblasti digitálního televizního vysílání na mobilní terminály ve standardech DVB-H/SH. Na konci této části jsou jasně popsány cíle této disertační práce. Druhá část práce je zaměřená na stručný popis blokového diagramu vysílačů v obou standardech DVB-H/SH. Dále jsou stručně popsány modely přenosových kanálů, které se používají pro modelování přenosu signálu. Stručný popis vytvořených aplikací, i s vývojovým diagramem, které jsou vhodné pro simulaci a analýzu přenosu v DVB-H/SH, jsou popsány v třetí části práce. Čtvrtá a nejdelší část této disertační práce se zabývá vyhodnocením získaných výsledků ze simulací a měření.This dissertation thesis deals with the analysis, simulation and measurement of the signal processing and transmission in DVB-H and DVB-SH standards. These standards are based on the assumption that signal reception is characterized by the transmission channels with echoes. These, so called fading channels, are mainly characterized by the path delays and path losses. Depending on the other, additional features (speed of the receiver, Doppler spectrum, etc.), it can be possible divided these channels onto three main groups: mobile, portable and fixed. Of course, signal transmission in different transmission channel models are affected differently. Therefore, it is needed found the optimal system parameters in both, DVB-H and DVB-SH standards, for the quality reception of the broadcasted mobile TV services, which is the main goal of this thesis. For this purpose, two appropriate applications (one for DVB-H and one for DVB-SH) with GUI were created in MATLAB, which enable simulated and analyzed the signal distortions in mobile, portable and fixed transmission scenarios. Moreover, these applications also contain a second application with GUI for the easy set and modification of the parameters of the used channel models. Therefore, it is possible to evaluate the effect of parameters of whole system and channel models on the achieved error rate (BER and MER) and quality of the transmission. In all mentioned transmission scenarios, the signal distortions (depending on the Carrier-to-Noise ratio) were obtained, evaluated and discussed in this dissertation thesis. Furthermore, in case of DVB-H, all obtained results from the simulations, were verified by the measuring. Differences between the obtained results (simulation and measuring) are also discussed. This dissertation thesis can be divided into four main parts. The first part of this dissertation thesis, after the short introduction, deals with present state-of-the-art and literature survey in mobile broadcast DVB-H/SH standards. At the end of this part are clearly outlined the main aims of this dissertation thesis. Second part is focused on the brief description of the functional block diagram of transmitters in both, DVB-H/SH standards. Furthermore, there are briefly described the transmission fading channel models, which are commonly used for the modeling of the signal transmission. The brief description of program applications with flowcharts, appropriate for the simulation of the transmission in the DVB-H/SH standards, are presented and described in the third part of this thesis. Finally, the fourth and longest part of this thesis is focused on the evaluation and comparison of obtained results from the simulations and measurements.

Design methodology for runtime reconfigurable FPGA: From high level specification down to implementation

In this paper we present an automatic design generation methodology for heterogeneous architectures composed of processors, DSPs and FPGAs. This methodology is based on an Adequation Algorithm Architecture where application is represented by a control data flow graph and architecture by an architecture graph. We focus on how to take into account specificities of partially reconfigurable components during the adequation process and for the design generation. We present a method which generates automatically the design for both fixed and partially reconfigurable parts of a FPGA. This method uses prefetching technic to minimize reconfiguration latency of runtime reconfiguration and buffer merging to minimize memory requirements of the generated design

Implementation of WiMAX physical layer baseband processing blocks in FPGA

This project thesis elaborates on designing a baseband processing blocks for Worldwide Interoperability for Microwave Access (WiMAX) physical layer using an FPGA. WiMAX provides broadband wireless access and uses OFDM as the essential modulation technique. The channel performance is badly affected due to synchronization mismatches between the transmitter and receiver ends so the transmitted signal received is not reliable as the OFDM deals with high data rate. This thesis includes the theory and concepts behind OFDM, WiMAX IEEE 802.16d standard and other blocks algorithms, its architectures used for designing as well as a presentation of how they are implemented. Here Altera’s FPGA has been used for targeting to the EP4SGX70HF35C2 device of the Stratix IV family. WiMAX use sophisticated digital signal processing techniques, which typically require a large number of mathematical computations. Here Stratix IV devices are ideally suited for these kinds of complex tasks because the DSP blocks have a combination of dedicated elements that perform multiplication, addition, subtraction, accumulation, summation, and dynamic shift operations. The WiMAX physical layer baseband processing architecture consists of various major modules which were simulated block wise in order to check its giving the correct output as required. The coding style used here is VHDL. The sub-blocks have been synthesized using Altera Quartus II v11. 0 and simulated using ModelSim Altera Edition 6.6d

Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies

Broadband Wireless Access technologies have significant market potential, especially the WiMAX protocol which can deliver data rates of tens of Mbps. Strong demand for high performance WiMAX solutions is forcing designers to seek help from multi-core processors that offer competitive advantages in terms of all performance metrics, such as speed, power and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an ASIC, coarse-grained dynamically reconfigurable processors are proving to be strong candidates for processing cores used in future high performance multi-core processor systems. This thesis investigates multi-core architectures with a newly emerging dynamically reconfigurable processor – RICA, targeting WiMAX physical layer applications. A novel master-slave multi-core architecture is proposed, using RICA processing cores. A SystemC based simulator, called MRPSIM, is devised to model this multi-core architecture. This simulator provides fast simulation speed and timing accuracy, offers flexible architectural options to configure the multi-core architecture, and enables the analysis and investigation of multi-core architectures. Meanwhile a profiling-driven mapping methodology is developed to partition the WiMAX application into multiple tasks as well as schedule and map these tasks onto the multi-core architecture, aiming to reduce the overall system execution time. Both the MRPSIM simulator and the mapping methodology are seamlessly integrated with the existing RICA tool flow. Based on the proposed master-slave multi-core architecture, a series of diverse homogeneous and heterogeneous multi-core solutions are designed for different fixed WiMAX physical layer profiles. Implemented in ANSI C and executed on the MRPSIM simulator, these multi-core solutions contain different numbers of cores, combine various memory architectures and task partitioning schemes, and deliver high throughputs at relatively low area costs. Meanwhile a design space exploration methodology is developed to search the design space for multi-core systems to find suitable solutions under certain system constraints. Finally, laying a foundation for future multithreading exploration on the proposed multi-core architecture, this thesis investigates the porting of a real-time operating system – Micro C/OS-II to a single RICA processor. A multitasking version of WiMAX is implemented on a single RICA processor with the operating system support

Energy-efficient wireless communication

In this chapter we present an energy-efficient highly adaptive network interface architecture and a novel data link layer protocol for wireless networks that provides Quality of Service (QoS) support for diverse traffic types. Due to the dynamic nature of wireless networks, adaptations in bandwidth scheduling and error control are necessary to achieve energy efficiency and an acceptable quality of service. In our approach we apply adaptability through all layers of the protocol stack, and provide feedback to the applications. In this way the applications can adapt the data streams, and the network protocols can adapt the communication parameters