Fiabilité de l’underfill et estimation de la durée de vie d’assemblages microélectroniques

Abstract : In order to protect the interconnections in flip-chip packages, an underfill material layer is used to fill the volumes and provide mechanical support between the silicon chip and the substrate. Due to the chip corner geometry and the mismatch of coefficient of thermal expansion (CTE), the underfill suffers from a stress concentration at the chip corners when the temperature is lower than the curing temperature. This stress concentration leads to subsequent mechanical failures in flip-chip packages, such as chip-underfill interfacial delamination and underfill cracking. Local stresses and strains are the most important parameters for understanding the mechanism of underfill failures. As a result, the industry currently relies on the finite element method (FEM) to calculate the stress components, but the FEM may not be accurate enough compared to the actual stresses in underfill. FEM simulations require a careful consideration of important geometrical details and material properties. This thesis proposes a modeling approach that can accurately estimate the underfill delamination areas and crack trajectories, with the following three objectives. The first objective was to develop an experimental technique capable of measuring underfill deformations around the chip corner region. This technique combined confocal microscopy and the digital image correlation (DIC) method to enable tri-dimensional strain measurements at different temperatures, and was named the confocal-DIC technique. This techique was first validated by a theoretical analysis on thermal strains. In a test component similar to a flip-chip package, the strain distribution obtained by the FEM model was in good agreement with the results measured by the confocal-DIC technique, with relative errors less than 20% at chip corners. Then, the second objective was to measure the strain near a crack in underfills. Artificial cracks with lengths of 160 μm and 640 μm were fabricated from the chip corner along the 45° diagonal direction. The confocal-DIC-measured maximum hoop strains and first principal strains were located at the crack front area for both the 160 μm and 640 μm cracks. A crack model was developed using the extended finite element method (XFEM), and the strain distribution in the simulation had the same trend as the experimental results. The distribution of hoop strains were in good agreement with the measured values, when the model element size was smaller than 22 μm to capture the strong strain gradient near the crack tip. The third objective was to propose a modeling approach for underfill delamination and cracking with the effects of manufacturing variables. A deep thermal cycling test was performed on 13 test cells to obtain the reference chip-underfill delamination areas and crack profiles. An artificial neural network (ANN) was trained to relate the effects of manufacturing variables and the number of cycles to first delamination of each cell. The predicted numbers of cycles for all 6 cells in the test dataset were located in the intervals of experimental observations. The growth of delamination was carried out on FEM by evaluating the strain energy amplitude at the interface elements between the chip and underfill. For 5 out of 6 cells in validation, the delamination growth model was consistent with the experimental observations. The cracks in bulk underfill were modelled by XFEM without predefined paths. The directions of edge cracks were in good agreement with the experimental observations, with an error of less than 2.5°. This approach met the goal of the thesis of estimating the underfill initial delamination, areas of delamination and crack paths in actual industrial flip-chip assemblies.Afin de protéger les interconnexions dans les assemblages, une couche de matériau d’underfill est utilisée pour remplir le volume et fournir un support mécanique entre la puce de silicium et le substrat. En raison de la géométrie du coin de puce et de l’écart du coefficient de dilatation thermique (CTE), l’underfill souffre d’une concentration de contraintes dans les coins lorsque la température est inférieure à la température de cuisson. Cette concentration de contraintes conduit à des défaillances mécaniques dans les encapsulations de flip-chip, telles que la délamination interfaciale puce-underfill et la fissuration d’underfill. Les contraintes et déformations locales sont les paramètres les plus importants pour comprendre le mécanisme des ruptures de l’underfill. En conséquent, l’industrie utilise actuellement la méthode des éléments finis (EF) pour calculer les composantes de la contrainte, qui ne sont pas assez précises par rapport aux contraintes actuelles dans l’underfill. Ces simulations nécessitent un examen minutieux de détails géométriques importants et des propriétés des matériaux. Cette thèse vise à proposer une approche de modélisation permettant d’estimer avec précision les zones de délamination et les trajectoires des fissures dans l’underfill, avec les trois objectifs suivants. Le premier objectif est de mettre au point une technique expérimentale capable de mesurer la déformation de l’underfill dans la région du coin de puce. Cette technique, combine la microscopie confocale et la méthode de corrélation des images numériques (DIC) pour permettre des mesures tridimensionnelles des déformations à différentes températures, et a été nommée le technique confocale-DIC. Cette technique a d’abord été validée par une analyse théorique en déformation thermique. Dans un échantillon similaire à un flip-chip, la distribution de la déformation obtenues par le modèle EF était en bon accord avec les résultats de la technique confocal-DIC, avec des erreurs relatives inférieures à 20% au coin de puce. Ensuite, le second objectif est de mesurer la déformation autour d’une fissure dans l’underfill. Des fissures artificielles d’une longueuer de 160 μm et 640 μm ont été fabriquées dans l’underfill vers la direction diagonale de 45°. Les déformations circonférentielles maximales et principale maximale étaient situées aux pointes des fissures correspondantes. Un modèle de fissure a été développé en utilisant la méthode des éléments finis étendue (XFEM), et la distribution des contraintes dans la simuation a montré la même tendance que les résultats expérimentaux. La distribution des déformations circonférentielles maximales était en bon accord avec les valeurs mesurées lorsque la taille des éléments était plus petite que 22 μm, assez petit pour capturer le grand gradient de déformation près de la pointe de fissure. Le troisième objectif était d’apporter une approche de modélisation de la délamination et de la fissuration de l’underfill avec les effets des variables de fabrication. Un test de cyclage thermique a d’abord été effectué sur 13 cellules pour obtenir les zones délaminées entre la puce et l’underfill, et les profils de fissures dans l’underfill, comme référence. Un réseau neuronal artificiel (ANN) a été formé pour établir une liaison entre les effets des variables de fabrication et le nombre de cycles à la délamination pour chaque cellule. Les nombres de cycles prédits pour les 6 cellules de l’ensemble de test étaient situés dans les intervalles d’observations expérimentaux. La croissance de la délamination a été réalisée par l’EF en évaluant l’énergie de la déformation au niveau des éléments interfaciaux entre la puce et l’underfill. Pour 5 des 6 cellules de la validation, le modèle de croissance du délaminage était conforme aux observations expérimentales. Les fissures dans l’underfill ont été modélisées par XFEM sans chemins prédéfinis. Les directions des fissures de bord étaient en bon accord avec les observations expérimentales, avec une erreur inférieure à 2,5°. Cette approche a répondu à la problématique qui consiste à estimer l’initiation des délamination, les zones de délamination et les trajectoires de fissures dans l’underfill pour des flip-chips industriels

Calcul du coefficient de constriction du flux thermique dans une matrice d'interconnexions en micro-électronique

La modélisation du flux thermique à travers une matrice d’interconnexions par éléments finis inclut de manière générale la modélisation complète d’au moins un élément d’interconnexion dans son intégralité. Ce procédé de discrétisation numérique étant très couteux en temps, des modèles mathématiques prenant en compte la géométrie de l’interconnexion et les propriétés des matériaux permettent de remplacer l’interconnexion et l’éventuel matériaux de remplissage par une couche équivalente homogène afin de diminuer le temps de calcul. Ces formules introduisent un paramètre appelé paramètre de constriction qui aide à représenter la résistance thermique due à la constriction du flux par l’élément d’interconnexion. Cependant, en comparant les modèles simplifiés aux modèles avec une modélisation complète de l’interconnexion, il est apparu que les résultats numériques obtenus présentent des écarts. Il en a donc été déduit que les formules pour calculer le paramètre de constriction n’étaient pas les mieux adaptées pour les géométries complexes des éléments d’interconnexions qu’il fallait représenter pour ce projet. Ce projet de maîtrise présente l’influence sur les simulations des différents paramètres géométriques (épaisseur de l’interconnexion, volume de l’élément d’interconnexion, densité du maillage défini par le nombre d’éléments d’interconnexions, présence d’un défaut d’alignement entre les deux parties à connecter) et des matériaux (différence de conductivité entre l’élément d’interconnexion et le matériau de remplissage)

Analysis and modeling of underfill flow driven by capillary action in flip-chip packaging

Flip-chip underfilling is a technology by which silica-filled epoxy resin is used to fill the micro-cavity between a silicon chip and a substrate, by dispensing the liquid encapsulant at elevated temperatures along the periphery of one or two sides of the chip and then allowing capillary action to draw the material into the gap. Since the chip, underfill material, and substrate solidify together as one unit, thermal stresses on solder joints during the temperature cycling (which are caused by a mismatch in the coefficients of thermal expansion between the silicon chip and the organic substrate) can be redistributed and transferred away from the fragile bump zone to a more strain-tolerant region. Modeling of the flow behaviour of a fluid in the underfill process is the key to this technology. One of the most important drawbacks in the existing models is inadequate treatment of non-Newtonian fluids in the underfill process in the development of both analytical models and numerical models. Another important drawback is the neglect of the presence of solder bumps in the existing analytical models. This thesis describes a study in which a proper viscosity constitutive equation, power-law model, is employed for describing the non-Newtonian fluid behaviour in flip-chip package. Based on this constitutive equation, two analytical models with closed-form solutions for predicting the fluid filling time and fluid flow front position with respect to time were derived. One model is for a setting with two parallel plates as an approximate to flip-chip package, while the other model is for a setting with two parallel plates within which an array of solder bumps are present. Furthermore, a numerical model using a general-purpose finite element package ANSYS was developed to predict the fluid flow map in two dimensions. The superiority of these models to the existing models (primarily those developed at Cornell University in 1997) is confirmed based on the results of the experiments conducted in this study. This thesis also presents a finding of the notion of critical clearance in the design of a flip-chip package through a careful simulation study using the models developed. The flip-chip package design should make the clearance between solder bumps larger than the critical clearance

Using confocal microscopy and digital image correlation to measure local strains around a chip corner and a crack front

Abstract: In a flip chip package, the chip corner areas which are embedded in the underfill material are often critical to the damage initiation, since a stress concentration usually exists at these locations. A high level of stress concentration often promotes crack initiation from the chip corner. In order to better understand the local deformation around chip corners and crack tips, a method based on laser scanning confocal microscopy combined with the digital image correlation (confocal-DIC) was developed to measure local strain directly in deformed, transparent objects. A transparent epoxy resin with alumina particle fillers was used in four different types of samples, which were fabricated for the purpose of validation. A non-constrained sample and a thin-layer sample were used to verify the isotropic thermal expansion and the strain gradients with respect to the depth, respectively. Results from both samples were in good agreements with the calculation from the coefficient of thermal expansion (CTE) and FEM simulations. Furthermore, the confocal-DIC technique was applied to measure the strain distribution near the chip corner area of a third sample replicating the geometry of a flip chip package. The measured maximum first principal strain was located at the chip corner, reaching 0.9 % at 60 °C, in a good agreement with the simulation results. The strain in front of the crack tip was also evaluated by a three-point bending test in a fourth test sample. The measured maximum strain was 5.8±0.7 %, corresponding to a relative error of only about 5 % compared to simulations for a round crack tip configuration. The averaging used in DIC lowers its spatial resolution and makes it difficult to capture higher strain gradients in small regions. However, the confocal-DIC approach appears to be able to provide reasonable results for evaluating the maximum strain and the full field strain distribution in tri-dimensional volumes with geometries, materials and dimensions which are very similar to those of actual flip chip microelectronic packages

A Novel Nanocomposite with Photo-Polymerization for Wafer Level Application

©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.A novel nanocomposite photo-curable material which can act both as a photoresist and a stress redistribution layer applied on the wafer level was synthesized and studied. In the experiments, 20-nm silica fillers were modified by a silane coupling agent through a hydrolysis and condensation reaction and then incorporated into the epoxy matrix. A photo-sensitive initiator was added into the formulation which can release cations after ultraviolet exposure and initiate the epoxy crosslinking reaction. The photo-crosslinking reaction of the epoxy made it a negative tone photoresist. The curing reaction of the nanocomposites was monitored by a differential scanning calorimeter with the photo-calorimetric accessory. The thermal mechanical properties of photo-cured nanocomposites thin film were also measured. It was found that the moduli change of the nanocomposites as the filler loading increasing did not follow the Mori–Tanaka model, which indicated that the nanocomposite was not a simple two-phase structure as the composite with micron size filler. The addition of nano-sized silica fillers reduced the thermal expansion and improved the stiffness of the epoxy, with only a minimal effect on the optical transparency of the epoxy, which facilitated the complete photo reaction in the epoxy

Thermo-Mechanical Reliability and Electrical Performance of Indium Interconnects and Under Bump Metallization

This thesis presents reliability analysis of indium interconnects and Under Bump Metallization (UBM) in flip chip devices. Flip chip assemblies with the use of bump interconnections are frequently used, especially in high density, three-dimensional electronic devices. Currently there are many methods for interconnect bumping, all of which require UBM. The UBM is required for interconnection, diffusion resistance and quality electrical contact between substrate and device. Bonded silicon test vehicles were comprised of Indium bumps and three UBM compositions: Ti/Ni/Au (200\xc5/1000\xc5/500\xc5), Ti/Ni (200\xc5/1000\xc5), Ni (1000\xc5). UBM and indium were deposited by evaporation and exposed to unbiased accelerated temperature cycling(-55°C to 125°C, 15°C/min ramp rate). Finite Element Analysis (FEA) simulations were used to gain understanding of non-linear strain behavior of indium interconnects during temperature cycling. Experimental testing coupled with FEA simulations facilitated cycle-to-failure calculations. FEA results show plastic strain concentrations within indium bump below failure limits. It has been demonstrated that fabrication of Ti/Ni/Au, Ti/Ni, and Ni UBM stacks performed reliably within infant mortality failure region

Effects of underfill material on solder deformation and damage in 3D packages

This paper will examine the effects of the introduction of a periodic boundary condition and the presence of underfill material on the stress and strain fields and evolution of failure of an FEA model that is representative of a solder joint in a 3D IC package. The model solder joint is placed between two silicon substrates in contact with through-silicon vias without any other devices or components attached. Differing solder joint thicknesses, both with and without underfill, will be examined to study the effect on the stress and strain fields as well as the evolution of failure in the solder joint. A dynamic loading on the FEA model will be used to examine the fracture pattern and mode of failure when the solder thickness is varied both with and without underfill material present

CFD Simulation Of Underfill Encapsulation Process In Flip Chip Packaging With Various Dispensing Methods

The major trend in electronic industry is to make the products smarter, lighter, functional and highly compact, at the same time cheaper. This trend has necessitated stringent packaging requirements and the flip-chip technology has emerged as a promising option to tackle this issue. However, a serious issue in flip-chip packaging is the difference in the coefficient of thermal expansion between the silicon chip and the organic substrate, which generates thermo-mechanical stresses and causes fatigue in solder joints. This problem is effectively solved by the underfill process in which the space between the silicon die and the PCB is filled with the underfill encapsulant that redistributes the induced stresses thereby enhancing the solder joints reliability

All-copper chip-to-substrate interconnects for high performance integrated circuit devices

In this work, all-copper connections between silicon microchips and substrates are developed. The semiconductor industry advances the transistor density on a microchip based on the roadmap set by Moore's Law. Communicating with a microprocessor which has nearly one billion transistors is a daunting challenge. Interconnects from the chip to the system (i.e. memory, graphics, drives, power supply) are rapidly growing in number and becoming a serious concern. Specifically, the solder ball connections that are formed between the chip itself and the package are challenging to make and still have acceptable electrical and mechanical performance. These connections are being required to increase in number, increase in power current density, and increase in off-chip operating frequency. Many of the challenges with using solder connections are limiting these areas. In order to advance beyond the limitations of solder for electrical and mechanical performance, a novel approach to creating all-copper connections from the chip-to-substrate has been developed. The development included characterizing the electroless plating and annealing process used to create the connections, designing these connections to be compatible with the stress requirements for fragile low-k devices, and finally by improving the plating/annealing process to become process time competitive with solder. It was found that using a commercially available electroless copper bath for the plating, followed by annealing at 180 C for 1 hour, the shear strength of the copper-copper bond was approximately 165 MPa. This work resulted in many significant conclusions about the mechanism for bonding in the all-copper process and the significance of materials and geometry on the mechanical design for these connections.Ph.D.Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, Jame

Experimental Study of Novel Materials and Module for Cryogenic (4K) Superconducting Multi-Chip Modules

The objectives of this proposal are to understand the science and technology of interfaces in the packaging of superconducting electronic (SCE) multichip modules (MCMs) at 4 K. The thermal management issue of the current SCE-MCMs was examined and the package assembly was optimized. A novel thermally conducting and electrically insulating nano-engineered polymer was developed for the thermal management of SCE-MCMs for 4 K cryogenic packaging. Finally, the nano-engineered polymer was integrated as underfill in a SCE-MCM and the thermal and electrical performance of SCE-MCM was demonstrated at 4 K. Niobium based superconducting electronics (SCE) are the fastest known digital logic which operate at 100GHz and greater. Nevertheless, the performance of the SCE device depends on the temperature of the SCE integrated circuits being maintained between 4.2 - 4.25 K. Additionally, as semiconductors are slowly approaching their performance limitations the SCE devices are viewed as a viable alternative for high end computing and commercial wireless applications. However, the successful implementation of SCE\u27s requires the demonstration of these devices in multichip module (MCM) architecture. Thus the stringent thermal constraint and the complex MCM architecture require an innovative method for thermal management which is addressed by the current research