Exploiting Inter- and Intra-Memory Asymmetries for Data Mapping in Hybrid Tiered-Memories

Modern computing systems are embracing hybrid memory comprising of DRAM and non-volatile memory (NVM) to combine the best properties of both memory technologies, achieving low latency, high reliability, and high density. A prominent characteristic of DRAM-NVM hybrid memory is that it has NVM access latency much higher than DRAM access latency. We call this inter-memory asymmetry. We observe that parasitic components on a long bitline are a major source of high latency in both DRAM and NVM, and a significant factor contributing to high-voltage operations in NVM, which impact their reliability. We propose an architectural change, where each long bitline in DRAM and NVM is split into two segments by an isolation transistor. One segment can be accessed with lower latency and operating voltage than the other. By introducing tiers, we enable non-uniform accesses within each memory type (which we call intra-memory asymmetry), leading to performance and reliability trade-offs in DRAM-NVM hybrid memory. We extend existing NVM-DRAM OS in three ways. First, we exploit both inter- and intra-memory asymmetries to allocate and migrate memory pages between the tiers in DRAM and NVM. Second, we improve the OS's page allocation decisions by predicting the access intensity of a newly-referenced memory page in a program and placing it to a matching tier during its initial allocation. This minimizes page migrations during program execution, lowering the performance overhead. Third, we propose a solution to migrate pages between the tiers of the same memory without transferring data over the memory channel, minimizing channel occupancy and improving performance. Our overall approach, which we call MNEME, to enable and exploit asymmetries in DRAM-NVM hybrid tiered memory improves both performance and reliability for both single-core and multi-programmed workloads.Comment: 15 pages, 29 figures, accepted at ACM SIGPLAN International Symposium on Memory Managemen

Efficient and realistic device modeling from atomic detail to the nanoscale

As semiconductor devices scale to new dimensions, the materials and designs become more dependent on atomic details. NEMO5 is a nanoelectronics modeling package designed for comprehending the critical multi-scale, multi-physics phenomena through efficient computational approaches and quantitatively modeling new generations of nanoelectronic devices as well as predicting novel device architectures and phenomena. This article seeks to provide updates on the current status of the tool and new functionality, including advances in quantum transport simulations and with materials such as metals, topological insulators, and piezoelectrics.Comment: 10 pages, 12 figure

Reliability Analysis of Radiation Tolerant Low Voltage CCCII Circuit For Space Applications

In this paper, the impact of radiation on the MOS devices is investigated on recently reported programmablesecond generation Current Controlled Conveyor (CCCII) wherein some updates are suggested to take Hot Carrier Injection, Bias Temperature Instability, and Time Dependent Dielectric Breakdown into account. As radiation is yet another important factor that causes change in threshold voltage, the transistors which are amenable to larger threshold shift and may lead to functional failure are identified first. Subsequently, three possibilities; uses of all thin oxide devices, all thick oxide devices, and mixed devices are being investigate and it is found that while using mixed devices, the circuit becomes functional at lower voltage without any effective increase in leakage current. Architecture is updated to enhance the performance of circuits under time-based ageing and radiation environment. The major challenge is to control dynamic leakage and radiative noise due to imposed radiation. All simulations are carried out using 28nm CMOS technology models in Cadence Virtuoso environment using ±1.0V supply voltage and results have been verified with post layout netlist. Proposed circuit can function at low voltage with the reduced degradation for 8 years at 25 °C consumes less area as compared to the existing CCCII circuit with 0.008 FIT value