Design and Implementation of the Quadrature Voltage Controlled Oscillator for Wireless Receiver Applications Utilizing 0.13 {Lm and 0.18 {Lm Deep Sub-Micron RF CMOS Technology

The field of high-frequency circuit design is receiving significant industrial attention due to variety of radio frequency and microwave applications. This work proposes the low power, low phase noise and low phase error quadrature voltage controlled oscillator (LP3 - QVCO) for wireless receiver applications. An enhanced investigation and design of the low power, low phase noise and low phase error quadrature voltage controlled oscillator (LP3 - QVCO) is carried out in comparison to conventional LC- QVCO. The design, implementation and characterization of the complementary LP3 - QVCO is carried out with the integration of 40 S1 source damping resistor (Rdmp), tail biasing resistor (Rtait) and multifinger gate width configuration of the pMOS varactors and 50 S1 impedance of common drain output buffers. The LP3 - QV CO implementation is carried out using 0.18 p,m, 6 metal, 1 poly, 1.8 V and 0.13 p,m, 8 metal, 1 poly, 1.2 V deep sub-micron CMOS and RF CMOS process technologies. The three different designs with the center frequencies of 2.8 GHz, 3.1 GHz and 3.8 GHz are implemented using 0.18 p,m CMOS and RF CMOS process technology. The remaining four designs with the center frequencies of 4.35 GHz and 5 GHz are implemented using 0.13 p,m RF CMOS process technologies. The LP3 - QVCO design exhibit the measured phase noise of -110.13 dBc/Hz and -108.54 dBc/Hz at the offset frequency of 1 MHz, with multifinger gate width configuration of pMOS varactor (3.125 p,m x 64 = 200 p,m) and (8 p,m x 25 = 200 p,m), respectively. The phase noise im provement of 1.63 dB is achieved in LP3 - QVCO design implemented with (3.125 I'm x 64 = 200 I'm) mult.ifinger gate width configuration of pMOS varactor in comparison to (8 f.tm x 25 = 200 f.tm). The measured center frequency of the LP3 - QVCO is 4.35 GHz with the frequency tuning range of 4.21 GHz to 4.44 GHz. Both LP3 - QVCO core power dissipation is 3.36 m W from 1.2 V de power supply. The measured phase error is less than 0.2'. The calculated figure of merit (FOM) is -177.6 dBc/Hz. The symmetrical spiral inductor is also used with patterned ground shield (PGS). The quality (Q) factor of inductor is 18.6 and is implemented using 0.13 f.tm RF CMOS process technology

Construction of classes of circuit-independent chaotic oscillatorsusing passive-only nonlinear devices

Two generic classes of chaotic oscillators comprising four different configurations are constructed. The proposed structures are based on the simplest possible abstract models of generic second-order RC sinusoidal oscillators that satisfy the basic condition for oscillation and the frequency of oscillation formulas. By linking these sinusoidal oscillator engines to simple passive first-order or second-order nonlinear composites, chaos is generated and the evolution of the two-dimensional sinusoidal oscillator dynamics into a higher dimensional state space is clearly recognized. We further discuss three architectures into which autonomous chaotic oscillators can be decomposed. Based on one of these architectures we classify a large number of the available chaotic oscillators and propose a novel reconstruction of the classical Chua’s circuit. The well-known Lorenz system of equations is also studied and a simplified model with equivalent dynamics, but containing no multipliers, is introduced

Survey on individual components for a 5 GHz receiver system using 130 nm CMOS technology

La intención de esta tesis es recopilar información desde un punto de vista general sobre los diferentes tipos de componentes utilizados en un receptor de señales a 5 GHz utilizando tecnología CMOS. Se ha realizado una descripción y análisis de cada uno de los componentes que forman el sistema, destacando diferentes tipos de configuraciones, figuras de mérito y otros parámetros. Se muestra una tabla resumen al final de cada sección, comparando algunos diseños que se han ido presentando a lo largo de los años en conferencias internacionales de la IEEE.The intention of this thesis is to gather information from an overview point about the different types of components used in a 5 GHz receiver using CMOS technology. A review of each of the components that form the system has been made, highlighting different types of configurations, figure of merits and parameters. A summary table is shown at the end of each section, comparing many designs that have been presented over the years at international conferences of the IEEE.Departamento de Ingeniería Energética y FluidomecánicaGrado en Ingeniería en Electrónica Industrial y Automátic

Design and Implementation of the Quadrature Voltage Controlled Oscillator for Wireless Receiver Applications Utilizing 0.13 {Lm and 0.18 {Lm Deep Sub-Micron RF CMOS Technology

The field of high-frequency circuit design is receiving significant industrial attention due to variety of radio frequency and microwave applications. This work proposes the low power, low phase noise and low phase error quadrature voltage controlled oscillator (LP3 - QVCO) for wireless receiver applications. An enhanced investigation and design of the low power, low phase noise and low phase error quadrature voltage controlled oscillator (LP3 - QVCO) is carried out in comparison to conventional LC- QVCO. The design, implementation and characterization of the complementary LP3 - QVCO is carried out with the integration of 40 S1 source damping resistor (Rdmp), tail biasing resistor (Rtait) and multifinger gate width configuration of the pMOS varactors and 50 S1 impedance of common drain output buffers. The LP3 - QV CO implementation is carried out using 0.18 p,m, 6 metal, 1 poly, 1.8 V and 0.13 p,m, 8 metal, 1 poly, 1.2 V deep sub-micron CMOS and RF CMOS process technologies. The three different designs with the center frequencies of 2.8 GHz, 3.1 GHz and 3.8 GHz are implemented using 0.18 p,m CMOS and RF CMOS process technology. The remaining four designs with the center frequencies of 4.35 GHz and 5 GHz are implemented using 0.13 p,m RF CMOS process technologies. The LP3 - QVCO design exhibit the measured phase noise of -110.13 dBc/Hz and -108.54 dBc/Hz at the offset frequency of 1 MHz, with multifinger gate width configuration of pMOS varactor (3.125 p,m x 64 = 200 p,m) and (8 p,m x 25 = 200 p,m), respectively. The phase noise im provement of 1.63 dB is achieved in LP3 - QVCO design implemented with (3.125 I'm x 64 = 200 I'm) mult.ifinger gate width configuration of pMOS varactor in comparison to (8 f.tm x 25 = 200 f.tm). The measured center frequency of the LP3 - QVCO is 4.35 GHz with the frequency tuning range of 4.21 GHz to 4.44 GHz. Both LP3 - QVCO core power dissipation is 3.36 m W from 1.2 V de power supply. The measured phase error is less than 0.2'. The calculated figure of merit (FOM) is -177.6 dBc/Hz. The symmetrical spiral inductor is also used with patterned ground shield (PGS). The quality (Q) factor of inductor is 18.6 and is implemented using 0.13 f.tm RF CMOS process technology

Construction of classes of circuit-independent chaotic oscillators using passive-only nonlinear devices

Two generic classes of chaotic oscillators comprising four different configurations are constructed. The proposed structures are based on the simplest possible abstract models of generic second-order RC sinusoidal oscillators that satisfy the basic condition for oscillation and the frequency of oscillation formulas. By linking these sinusoidal oscillator engines to simple passive first-order or second-order nonlinear composites, chaos is generated and the evolution of the two-dimensional sinusoidal oscillator dynamics into a higher dimensional state space is clearly recognized. We further discuss three architectures into which autonomous chaotic oscillators can be decomposed. Based on one of these architectures we classify a large number of the available chaotic oscillators and propose a novel reconstruction of the classical Chua's circuit. The well-known Lorenz system of equations is also studied and a simplified model with equivalent dynamics, but containing no multipliers, is introduce

SiGe based multiple-phase VCO operating for mm-wave frequencies

The ever-increasing demand for higher speed in wireless consumer applications has increased the interest in the unlicensed spectrum of 7 GHz around 60 GHz. The high atmospheric oxygen absorption at 60 GHz and small size of the antennas at this frequency requires the use of integrated phased-array systems to overcome the deficiencies of lossy channels at these frequencies. The phased arrays combine signals from multiple paths to obtain higher receiver sensitivity and directivity. The system thus requires phase-shifted voltage-controlled oscillator (VCO) signals to implement phase shifting in the local-oscillator (LO) path. In this research, the vector sum method to generate various phases of the signal at 60 GHz was investigated for its suitability in phased-array systems. The main focus was on improving the phase noise performance of the VCO. The VCO was implemented using a fully differential common-collector Colpitts oscillator in the cascode configuration, which was found to be the VCO configuration with acceptable phase noise performance and stability in the millimetre-wave range. The research focus was on modelling the phase noise of the VCO, and was performed by identifying the impulse sensitivity function for various noise sources, followed by analysing its effect on the linear time varying (LTV) model of the oscillators. The analysis led to a closed-form expression for the phase noise of the oscillator in terms of process and design parameters. The design was then optimised in terms of identified parameters to attain minimum phase noise. The phase noise expression using LTV theory and SpectreRF simulations reported the same optimum value for the design parameter, of around 0.3 for the capacitor ratio. The simulation results utilising the vector sum phase shifting method to generate multiple phase oscillator signals suggest its suitability in implementing phased-array systems in the millimetre-wave range. The vector sum was realised by generating quadrature signals from the oscillator using hybrid couplers. Variable gain amplifiers (VGAs) based on Gilbert mixer topology were used to combine the in-phase and quadrature phase signals to generate the phase-shifted oscillator signal. The gains of the VGAs were linearised by using a pre-distortion circuit, which was an inverse tanh cell. A fully differential 60 GHz VCO was fabricated using a SiGe process with a fT of 200 GHz. The fabricated integrated circuit (IC) measured at the wafer level had a centre frequency of 52.8 GHz and a tuning range of 7 GHz. It demonstrated a phase noise performance of -98.9 dBc/Hz at 1 MHz offset and a power dissipation of 140 mW, thus providing a VCO figure of merit of 172 dBc/Hz. It delivered a differential output power of 8 dBm and the IC occupied an area of 0.54 mm2, including the bondpads. It was thus concluded that a 10 % design margin for the tuning range is required while using SiGe BiCMOS technology. The simulation results demonstrate that the VCO, along with an active interpolator, provides a range of phase-shifted signals from 0° to 360° in steps of 22.5° for various gain settings of the VGAs. The power dissipation of the active interpolator is around 60 mW and the system could thus be employed in LO path shifting architecture of the phased arrays with increased power consumption.Thesis (PhD)--University of Pretoria, 2013.Electrical, Electronic and Computer Engineeringunrestricte

Analog Implementation of Fractional-Order Elements and Their Applications

With advancements in the theory of fractional calculus and also with widespread engineering application of fractional-order systems, analog implementation of fractional-order integrators and differentiators have received considerable attention. This is due to the fact that this powerful mathematical tool allows us to describe and model a real-world phenomenon more accurately than via classical “integer” methods. Moreover, their additional degree of freedom allows researchers to design accurate and more robust systems that would be impractical or impossible to implement with conventional capacitors. Throughout this thesis, a wide range of problems associated with analog circuit design of fractional-order systems are covered: passive component optimization of resistive-capacitive and resistive-inductive type fractional-order elements, realization of active fractional-order capacitors (FOCs), analog implementation of fractional-order integrators, robust fractional-order proportional-integral control design, investigation of different materials for FOC fabrication having ultra-wide frequency band, low phase error, possible low- and high-frequency realization of fractional-order oscillators in analog domain, mathematical and experimental study of solid-state FOCs in series-, parallel- and interconnected circuit networks. Consequently, the proposed approaches in this thesis are important considerations in beyond the future studies of fractional dynamic systems

Simple Three-Input Single-Output Current-Mode Universal Filter Using Single VDCC

This paper presents a second-order current-mode filter with three-inputs and single-output current using single voltage differencing current conveyors (VDCC) along with one resistor and two grounded capacitors. The design of presented filter emphasizes on the use of a single active element without the multiple terminals VDCC which is convenient to implement the VDCC using commercially available IC for the practical test. Also, it can reduce the current tracking error at current output port and can reduce the number of transistor in the VDCC. The proposed filter can realize all the five generic filter responses, namely, band-pass (BP), band-reject (BR), low-pass (LP), high-pass (HP), and all-pass (AP) functions from the same configuration under various conditions in terms of three input current signals. Furthermore, the natural frequency and quality factor are electronically controlled. The output current node exhibits high impedance. Besides, the non-ideal case is also investigated. The simulation and experimental results using VDCC constructed from commercially available IC can validate the theoretical analyses