Design guidelines for spatial modulation

A new class of low-complexity, yet energyefficient Multiple-Input Multiple-Output (MIMO) transmission techniques, namely the family of Spatial Modulation (SM) aided MIMOs (SM-MIMO) has emerged. These systems are capable of exploiting the spatial dimensions (i.e. the antenna indices) as an additional dimension invoked for transmitting information, apart from the traditional Amplitude and Phase Modulation (APM). SM is capable of efficiently operating in diverse MIMO configurations in the context of future communication systems. It constitutes a promising transmission candidate for large-scale MIMO design and for the indoor optical wireless communication whilst relying on a single-Radio Frequency (RF) chain. Moreover, SM may also be viewed as an entirely new hybrid modulation scheme, which is still in its infancy. This paper aims for providing a general survey of the SM design framework as well as of its intrinsic limits. In particular, we focus our attention on the associated transceiver design, on spatial constellation optimization, on link adaptation techniques, on distributed/ cooperative protocol design issues, and on their meritorious variants

Cross-layer network lifetime optimization considering transmit and signal processing power in WSNs

Maintaining high energy efficiency is essential for increasing the lifetime of wireless sensor networks (WSNs), where the battery of the sensor nodes cannot be routinely replaced. Nevertheless, the energy budget of the WSN strictly relies on the communication parameters, where the choice of both the transmit power as well as of the modulation and coding schemes (MCSs) plays a significant role in maximizing the network lifetime (NL). In this paper, we optimize the NL of WNSs by analysing the impact of the physical layer parameters as well as of the signal processing power (SPP) P_sp on the NL. We characterize the underlying trade-offs between the NL and bit error ratio (BER) performance for a predetermined set of target signal-to-interference-plus-noise ratio (SINR) values and for different MCSs using periodic transmit-time slot (TS) scheduling in interference-limited WSNs. For a per-link target BER requirement (PLBR) of 10^?3, our results demonstrate that a ’continuous-time’ NL in the range of 0.58?4.99 years is achieved depending on the MCSs, channel configurations, and SPP

Energy-delay bounds analysis in wireless multi-hop networks with unreliable radio links

Energy efficiency and transmission delay are very important parameters for wireless multi-hop networks. Previous works that study energy efficiency and delay are based on the assumption of reliable links. However, the unreliability of the channel is inevitable in wireless multi-hop networks. This paper investigates the trade-off between the energy consumption and the end-to-end delay of multi-hop communications in a wireless network using an unreliable link model. It provides a closed form expression of the lower bound on the energy-delay trade-off for different channel models (AWGN, Raleigh flat fading and Nakagami block-fading) in a linear network. These analytical results are also verified in 2-dimensional Poisson networks using simulations. The main contribution of this work is the use of a probabilistic link model to define the energy efficiency of the system and capture the energy-delay trade-offs. Hence, it provides a more realistic lower bound on both the energy efficiency and the energy-delay trade-off since it does not restrict the study to the set of perfect links as proposed in earlier works

A virtual MIMO dual-hop architecture based on hybrid spatial modulation

International audienceIn this paper, we propose a novel Virtual Multiple-Input-Multiple-Output (VMIMO) architecture based on the concept of Spatial Modulation (SM). Using a dual-hop and Decode-and-Forward protocol, we form a distributed system, called Dual-Hop Hybrid SM (DH-HSM). DH-HSM conveys information from a Source Node (SN) to a Destination Node (DN) via multiple Relay Nodes (RNs). The spatial position of the RNs is exploited for transferring information in addition to, or even without, a conventional symbol. In order to increase the performance of our architecture, while keeping the complexity of the RNs and DN low, we employ linear precoding using Channel State Information (CSI) at the SN. In this way, we form a Receive-Spatial Modulation (R-SM) pattern from the SN to the RNs, which is able to employ a centralized coordinated or a distributed uncoordinated detection algorithm at the RNs. In addition, we focus on the SN and propose two regularized linear precoding methods that employ realistic Imperfect Channel State Information at the Transmitter. The power of each precoder is analyzed theoretically. Using the Bit Error Rate (BER) metric, we evaluate our architecture against the following benchmark systems: 1) single relay; 2) best relay selection; 3) distributed Space Time Block Coding (STBC) VMIMO scheme; and 4) the direct communication link. We show that DH-HSM is able to achieve significant Signal-to-Noise Ratio (SNR) gains, which can be as high as 10.5 dB for a very large scale system setup. In order to verify our simulation results, we provide an analytical framework for the evaluation of the Average Bit Error Probability (ABEP)

Contrasting space-time schemes for MIMO FSO systems with non-coherent modulation

International audienc

Low Power Decoding Circuits for Ultra Portable Devices

A wide spread of existing and emerging battery driven wireless devices do not necessarily demand high data rates. Rather, ultra low power, portability and low cost are the most desired characteristics. Examples of such applications are wireless sensor networks (WSN), body area networks (BAN), and a variety of medical implants and health-care aids. Being small, cheap and low power for the individual transceiver nodes, let those to be used in abundance in remote places, where access for maintenance or recharging the battery is limited. In such scenarios, the lifetime of the battery, in most cases, determines the lifetime of the individual nodes. Therefore, energy consumption has to be so low that the nodes remain operational for an extended period of time, even up to a few years. It is known that using error correcting codes (ECC) in a wireless link can potentially help to reduce the transmit power considerably. However, the power consumption of the coding-decoding hardware itself is critical in an ultra low power transceiver node. Power and silicon area overhead of coding-decoding circuitry needs to be kept at a minimum in the total energy and cost budget of the transceiver node. In this thesis, low power approaches in decoding circuits in the framework of the mentioned applications and use cases are investigated. The presented work is based on the 65nm CMOS technology and is structured in four parts as follows: In the first part, goals and objectives, background theory and fundamentals of the presented work is introduced. Also, the ECC block in coordination with its surrounding environment, a low power receiver chain, is presented. Designing and implementing an ultra low power and low cost wireless transceiver node introduces challenges that requires special considerations at various levels of abstraction. Similarly, a competitive solution often occurs after a conclusive design space exploration. The proposed decoder circuits in the following parts are designed to be embedded in the low power receiver chain, that is introduced in the first part. Second part, explores analog decoding method and its capabilities to be embedded in a compact and low power transceiver node. Analog decod- ing method has been theoretically introduced over a decade ago that followed with early proof of concept circuits that promised it to be a feasible low power solution. Still, with the increased popularity of low power sensor networks, it has not been clear how an analog decoding approach performs in terms of power, silicon area, data rate and integrity of calculations in recent technologies and for low data rates. Ultra low power budget, small size requirement and more relaxed demands on data rates suggests a decoding circuit with limited complexity. Therefore, the four-state (7,5) codes are considered for hardware implementation. Simulations to chose the critical design factors are presented. Consequently, to evaluate critical specifications of the decoding circuit, three versions of analog decoding circuit with different transistor dimensions fabricated. The measurements results reveal different trade-off possibilities as well as the potentials and limitations of the analog decoding approach for the target applications. Measurements seem to be crucial, since the available computer-aided design (CAD) tools provide limited assistance and precision, given the amount of calculations and parameters that has to be included in the simulations. The largest analog decoding core (AD1) takes 0.104mm2 on silicon and the other two (AD2 and AD3) take 0.035mm2 and 0.015mm2, respectively. Consequently, coding gain in trade-off with silicon area and throughput is presented. The analog decoders operate with 0.8V supply. The achieved coding gain is 2.3 dB at bit error rates (BER)=0.001 and 10 pico-Joules per bit (pJ/b) energy efficiency is reached at 2 Mbps. Third part of this thesis, proposes an alternative low power digital decoding approach for the same codes. The desired compact and low power goal has been pursued by designing an equivalent digital decoding circuit that is fabricated in 65nm CMOS technology and operates in low voltage (near-threshold) region. The architecture of the design is optimized in system and circuit levels to propose a competitive digital alternative. Similarly, critical specifications of the decoder in terms of power, area, data rate (speed) and integrity are reported according to the measurements. The digital implementation with 0.11mm2 area, consumes minimum energy at 0.32V supply which gives 9 pJ/b energy efficiency at 125 kb/s and 2.9 dB coding gain at BER=0.001. The forth and last part, compares the proposed design alternatives based on the fabricated chips and the results attained from the measurements to conclude the most suitable solution for the considered target applications. Advantages and disadvantages of both approaches are discussed. Possible extensions of this work is introduced as future work

Quantifying Potential Energy Efficiency Gain in Green Cellular Wireless Networks

Conventional cellular wireless networks were designed with the purpose of providing high throughput for the user and high capacity for the service provider, without any provisions of energy efficiency. As a result, these networks have an enormous Carbon footprint. In this paper, we describe the sources of the inefficiencies in such networks. First we present results of the studies on how much Carbon footprint such networks generate. We also discuss how much more mobile traffic is expected to increase so that this Carbon footprint will even increase tremendously more. We then discuss specific sources of inefficiency and potential sources of improvement at the physical layer as well as at higher layers of the communication protocol hierarchy. In particular, considering that most of the energy inefficiency in cellular wireless networks is at the base stations, we discuss multi-tier networks and point to the potential of exploiting mobility patterns in order to use base station energy judiciously. We then investigate potential methods to reduce this inefficiency and quantify their individual contributions. By a consideration of the combination of all potential gains, we conclude that an improvement in energy consumption in cellular wireless networks by two orders of magnitude, or even more, is possible.Comment: arXiv admin note: text overlap with arXiv:1210.843