Experimental study of artificial neural networks using a digital memristor simulator

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a fully digital implementation of a memristor hardware simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field programmable gate array (FPGA) families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks (ANNs), implementing examples of associative memory and unsupervised learning of spatio-temporal correlations in parallel input streams using a simplified STDP. We provide the full circuit schematics of all our digital circuit designs and comment on the required hardware resources and their scaling trends, thus presenting a design framework for applications based on our hardware simulator.Peer ReviewedPostprint (author's final draft

HW/SW Co-Simulation System for Enhancing Hardware-in-the-Loop of Power Converter Digital Controllers

Digital controllers of power converters are more and more implemented in FPGAs due to the increasing complexity of current control algorithms, higher switching frequencies, and concurrence requirements. System behavior depends not only on the control algorithm but also on the implementation issues. Thus, closed-loop controller evaluation at early design stages is a main concern. In this paper, a new hardware-in-the-loop method is proposed. It profits from FPGAs and their design tools in order to validate the closed-loop power converter before prototyping the power stage. The proposed solution presents a general architecture that does not depend on specific vendors or CAD tools, but it uses those utilized for the final implementation of the controller. A case study is presented with a given implementation of the proposed solution. Comparisons with existing alternatives show the advantages of our approach

An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links

Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation on silicon is, the higher the communication performance of the hosting platforms has to be. Many times the bottleneck of these system implementations is not on the performance inside a chip or a board, but in the communication between boards. This paper describes a novel modular Address-Event-Representation (AER) FPGA-based (Spartan6) infrastructure PCB (the AER-Node board) with 2.5Gbps LVDS high speed serial links over SATA cables that offers a peak performance of 32-bit 62.5Meps (Mega events per second) on board-to-board communications. The board allows back compatibility with parallel AER devices supporting up to x2 28-bit parallel data with asynchronous handshake. These boards also allow modular expansion functionality through several daughter boards. The paper is focused on describing in detail the LVDS serial interface and presenting its performance.Ministerio de Ciencia e Innovación TEC2009-10639-C04-02/01Ministerio de Economía y Competitividad TEC2012-37868-C04-02/01Junta de Andalucía TIC-6091Ministerio de Economía y Competitividad PRI-PIMCHI-2011-076

Emulation of Circuits under Test Using Low-Cost Embedded Platforms

Electrical engineering education requires the development of the specific ability and skills to address the design and assembly of practical electronic circuits, as well as the use of advanced electronic instrumentation. However, for electronic instrumentation courses or any other related specialty that pursues to gain expertise testing a physical system, the circuit assembly process itself can represent a bottleneck in a practical session. The time dedicated to the circuit assembly is subtracted both to the measurements and the final decision-making time. Therefore, the student's practical experience is limited. This article presents a reconfigurable physical system based on the Arduino (TM) shield pin-out, which (after specific programming) can virtually behave as a device under test to carry out measurement procedures on it, emulating any system or process. Although it has been mainly oriented to the Arduino boards, it is possible to add different control devices with a connector compatible. The user does not need to assemble any circuit. Our approach does not only pursue the correct instrument handling as a goal, but it also immerses the student in the context of the functional theory of the proposed circuit under test. Consequently, the same emulation platform can be utilized for other techno-scientific specialties, such as electrical engineering, automatic control systems or physics courses. Besides that, it is a compact product that can be adapted to the needs of any teaching institution.This work was performed as an innovation and teaching improvement project and supported by grant SOL-201700083174-TRA from Vicerrectorado de Recursos Docentes y de la Comunicacion, University of Cadiz

CABE : a cloud-based acoustic beamforming emulator for FPGA-based sound source localization

Microphone arrays are gaining in popularity thanks to the availability of low-cost microphones. Applications including sonar, binaural hearing aid devices, acoustic indoor localization techniques and speech recognition are proposed by several research groups and companies. In most of the available implementations, the microphones utilized are assumed to offer an ideal response in a given frequency domain. Several toolboxes and software can be used to obtain a theoretical response of a microphone array with a given beamforming algorithm. However, a tool facilitating the design of a microphone array taking into account the non-ideal characteristics could not be found. Moreover, generating packages facilitating the implementation on Field Programmable Gate Arrays has, to our knowledge, not been carried out yet. Visualizing the responses in 2D and 3D also poses an engineering challenge. To alleviate these shortcomings, a scalable Cloud-based Acoustic Beamforming Emulator (CABE) is proposed. The non-ideal characteristics of microphones are considered during the computations and results are validated with acoustic data captured from microphones. It is also possible to generate hardware description language packages containing delay tables facilitating the implementation of Delay-and-Sum beamformers in embedded hardware. Truncation error analysis can also be carried out for fixed-point signal processing. The effects of disabling a given group of microphones within the microphone array can also be calculated. Results and packages can be visualized with a dedicated client application. Users can create and configure several parameters of an emulation, including sound source placement, the shape of the microphone array and the required signal processing flow. Depending on the user configuration, 2D and 3D graphs showing the beamforming results, waterfall diagrams and performance metrics can be generated by the client application. The emulations are also validated with captured data from existing microphone arrays.</jats:p