126 research outputs found

    Multi-rate real-time simulation of modular multilevel converter using CPU and FPGA

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    This thesis presents the real-time simulation of a modular multilevel converter (MMC) using Field Programmable Gates Array (FPGA). Undertaking such a project raises challenges due to the very high number of components in MMC. The choice of the hardware used is justified by this particular problematic. Using FPGA, a very large number of inputs and outputs can be easily managed. By simulating the converter on FPGA reduces latency and the delays between the IOs and the MMC. It also allows using very small time-step ensuring accuracy for pulses detection. Only the converter is simulated on FPGA and the remaining component of the simulation, such as the AC system and its distribution network are simulated on CPU. Doing so gives the user access to large library of component from commercial software. Using two distinct platforms, CPU and FPGA, then requires the model not only to be decoupled, but also to use different sampling time. This thesis debuts by a presentation of the problematic. Then, the required sampling time for accurate simulation of MMC is demonstrated. In order to achieve such a small time-step, a decoupling method and its validation is proposed. The method is then generalized and applied to multi-rate simulation. Using those methods, a details implementation of the converter, using OPAL-RT technologies real-time simulator, is given. Finally, numerical and experimental validation of this model are presented

    Co-simulation techniques based on virtual platforms for SoC design and verification in power electronics applications

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    En las últimas décadas, la inversión en el ámbito energético ha aumentado considerablemente. Actualmente, existen numerosas empresas que están desarrollando equipos como convertidores de potencia o máquinas eléctricas con sistemas de control de última generación. La tendencia actual es usar System-on-chips y Field Programmable Gate Arrays para implementar todo el sistema de control. Estos dispositivos facilitan el uso de algoritmos de control más complejos y eficientes, mejorando la eficiencia de los equipos y habilitando la integración de los sistemas renovables en la red eléctrica. Sin embargo, la complejidad de los sistemas de control también ha aumentado considerablemente y con ello la dificultad de su verificación. Los sistemas Hardware-in-the-loop (HIL) se han presentado como una solución para la verificación no destructiva de los equipos energéticos, evitando accidentes y pruebas de alto coste en bancos de ensayo. Los sistemas HIL simulan en tiempo real el comportamiento de la planta de potencia y su interfaz para realizar las pruebas con la placa de control en un entorno seguro. Esta tesis se centra en mejorar el proceso de verificación de los sistemas de control en aplicaciones de electrónica potencia. La contribución general es proporcionar una alternativa a al uso de los HIL para la verificación del hardware/software de la tarjeta de control. La alternativa se basa en la técnica de Software-in-the-loop (SIL) y trata de superar o abordar las limitaciones encontradas hasta la fecha en el SIL. Para mejorar las cualidades de SIL se ha desarrollado una herramienta software denominada COSIL que permite co-simular la implementación e integración final del sistema de control, sea software (CPU), hardware (FPGA) o una mezcla de software y hardware, al mismo tiempo que su interacción con la planta de potencia. Dicha plataforma puede trabajar en múltiples niveles de abstracción e incluye soporte para realizar co-simulación mixtas en distintos lenguajes como C o VHDL. A lo largo de la tesis se hace hincapié en mejorar una de las limitaciones de SIL, su baja velocidad de simulación. Se proponen diferentes soluciones como el uso de emuladores software, distintos niveles de abstracción del software y hardware, o relojes locales en los módulos de la FPGA. En especial se aporta un mecanismo de sincronizaron externa para el emulador software QEMU habilitando su emulación multi-core. Esta aportación habilita el uso de QEMU en plataformas virtuales de co-simulacion como COSIL. Toda la plataforma COSIL, incluido el uso de QEMU, se ha analizado bajo diferentes tipos de aplicaciones y bajo un proyecto industrial real. Su uso ha sido crítico para desarrollar y verificar el software y hardware del sistema de control de un convertidor de 400 kVA

    Modeling of Direct Current Grid Equipment for the Simulation and Analysis of Electromagnetic Transients

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    RÉSUMÉ Les transmissions à base de courant continu sont capables de répondre mieux que les transmissions traditionnelles à base de courant alternatif aux enjeux de nos jours tels que l’intégration des énergies renouvelables, les difficultés avec l’installation des nouvelles lignes aériennes pour les raisons socio-environnementaux, la gestion des flux de puissance sur le réseau électrique. Ceci est grâce aux systèmes de contrôle performants et rapides, à un niveau de fiabilité accrue des composants utilisés, à l’efficacité énergétique des technologies de pointe, telles que les convertisseurs modulaires multiniveaux (Modular Multilevel Converter ou MMC en anglais). Ces avantages ont contribué à une croissance rapide du nombre de transmissions à courant continu à travers le monde dans les dernières années, avec les plans d’établir des réseaux multi-terminaux d’un niveau supérieur aux réseaux électriques traditionnels dans le but de les renforcer. Les outils de simulation numériques sont nécessaires pour faciliter et accélérer la mise en œuvre de ce type de projets d’envergure. Ils permettent d’analyser et d’étudier les systèmes électriques de plus en plus complexes et par conséquent d’éviter les problèmes opérationnels, d’augmenter la fiabilité et l’efficacité des réseaux électriques. La complexité accrue des réseaux électriques modernes qui contiennent les composants à base de l’électronique de puissance tels que les liaisons à courant continu exige une recherche sur les outils de simulation et les modèles avancés. Ainsi, cette thèse se focalise sur le développement d’un cadre pour les simulations précises et rapides des liaisons à courant continu. À la suite d’une revue de la littérature il est démontré que la modélisation des MMCs a un impact particulièrement important sur la précision et l’accélération des simulations et par conséquent une grande partie de cette thèse est dédiée aux différentes méthodes pour réduire le temps de simulation et améliorer la précision des résultats dans les études avec les MMCs. Le cœur du sujet commence par la présentation de la modélisation des MMC hybrides et leurs systèmes de contrôle. Les modèles sont classés en quatre catégories selon le niveau de précision : le modèle détaillé permet de représenter les non-linéarités au niveau des composants semiconducteurs.----------ABSTRACT Compared to the traditional alternating current technology-based electrical grids, High-Voltage Direct Current (HVDC) transmission systems can more effectively respond to the challenges of the modern power grid related to the integration of renewable energy sources, difficulty to install new overhead lines due to socio-environmental reasons, and power flow management. This is mainly due to high performance of control systems, fast response times, reliable components and energy efficiency of the state-of-the-art HVDC technologies of today, such as the Modular Multilevel Converter (MMC). These advantages have contributed to the rapid growth in the number of HVDC projects in recent years with plans of having overlay HVDC grids that can reinforce the existing electrical grids. To facilitate and accelerate the implementation of large-scale HVDC projects, it is required to use numerical simulation tools. Such tools allow to perform advanced analysis of involved electrical systems for preventing operating problems, increasing robustness and efficiency in power grids. The increased level of complexity of modern power grids with power electronics-based components, such as HVDC, requires research on advanced simulation tools and models. Therefore, this thesis aims to develop a framework allowing for accurate modeling and fast simulations of HVDC projects. After analysis of existing literature, the areas with high potential impact on accuracy and acceleration of electromagnetic transient simulations are found, and it is the modeling of MMCs that is considered in this thesis. Thus, a significant part of this thesis is dedicated to research on efficient modeling techniques that allow to reduce simulation time and improve accuracy for MMC-based HVDC systems. The modeling aspects and control systems of hybrid MMCs are presented first. The MMC models used in electromagnetic transient simulations are grouped into four categories. The detailed model represents the nonlinear current-voltage characteristics of semiconductor switches. The detailed equivalent model represents the switches as two-value resistances: a small value for the closed state and a large value for the open state. The arm equivalent model assumes all capacitors in each arm have identical voltages, so a single equivalent capacitor is used to represent the whole arm, thus greatly reducing the computational burden of the model

    Design and Control of Power Converters 2019

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    In this book, 20 papers focused on different fields of power electronics are gathered. Approximately half of the papers are focused on different control issues and techniques, ranging from the computer-aided design of digital compensators to more specific approaches such as fuzzy or sliding control techniques. The rest of the papers are focused on the design of novel topologies. The fields in which these controls and topologies are applied are varied: MMCs, photovoltaic systems, supercapacitors and traction systems, LEDs, wireless power transfer, etc

    Design and test of a neural microprocessor

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    En aquest projecte, es dissenya un microprocessador neuronal per ser implementat en FPGAs. Aquesta tecnologia consisteix en un processador softcore basat en RISC-V descrit amb SystemVerilog que s'utilitza per controlar un coprocessador encarregat d'executar una xarxa neuronal spiking amb propagació directa descrita amb VHDL. El control es fa amb senyals que es generen a partir d'instruccions SIMD personalitzades definides en una extensió del conjunt d’instruccions RSIC-V. Per fer-ho, es modifica el processador de manera que pugui detectar i descodificar les noves instruccions emmagatzemades a la seva memòria de programa. Per facilitar la tasca de definir el contingut de la memòria del programa, s'utilitza un codi escrit en C i es desenvolupa un conjunt d'instruccions C personalitzades. Aquestes instruccions es basen en l'ús de macros i inline assembly, i la seva finalitat és facilitar i permetre l'ús de les instruccions personalitzades RISC-V en el codi d'alt nivell. Per demostrar el correcte funcionament del projecte, se simula el microprocessador neuronal i després es prova a l'FPGA d'una placa de desenvolupament Nexys 4, amb el coprocessador implementat per resoldre el problema XOR. La implementació del coprocessador es replica amb C i s'executa a l'FPGA utilitzant només el processador predeterminat sense modificar. Finalment, els resultats s'analitzen i es comparen per determinar les compensacions entre els dos enfocaments en termes de temps d'execució, consum d'energia i espai utilitzat.En este proyecto, se diseña un microprocesador neuronal para su implementación en FPGAs. Esta tecnología consiste en un procesador softcore basado en RISC-V descrito con SystemVerilog que se utiliza para controlar a un coprocesador encargado de ejecutar una red neuronal spiking con propagación directa descrita con VHDL. El control se realiza con señales que se generan a partir de instrucciones SIMD personalizadas definidas en una extensión del conjunto de instrucciones RSIC-V. Para ello, se modifica el procesador de forma que pueda detectar y descodificar las nuevas instrucciones almacenadas en su memoria de programa. Para facilitar la tarea de definir el contenido de la memoria del programa, se utiliza un código escrito en C y se desarrolla un conjunto de instrucciones C personalizadas. Estas instrucciones se basan en el uso de macros e inline assembly, y su finalidad es facilitar y permitir el uso de las instrucciones personalizadas RISC-V en el código de alto nivel. Para demostrar el correcto funcionamiento del proyecto, se simula el microprocesador neuronal y después se prueba en la FPGA de una placa de desarrollo Nexys 4, con el coprocesador implementado para resolver el problema XOR. La implementación del coprocesador se replica con C y se ejecuta en la FPGA utilizando sólo el procesador predeterminado sin modifcar. Por último, los resultados se analizan y se comparan para determinar las compensaciones entre ambos enfoques en términos de tiempo de ejecución, consumo de energía y espacio utilizado.In this project, a neural microprocessor is designed to be implemented in FPGAs. This technology consists of a RISC-V-based soft processor described in SystemVerilog that is used to control a coprocessor in charge of executing a feedforward spiking neural network described in VHDL. The control is done with signals that are generated from custom-designed SIMD instructions defined in a RISC-V ISA extension. To do it, the processor is modified such that it can detect and decode the new instructions stored in its program memory. To facilitate the task of defining the program memory contents, a code written in C is used and a set of custom C instructions is developed. These instructions are based on the use of macros and inline assembly, and their purpose is to facilitate and allow the use of the RISC-V custom instructions in the high-level code. To demonstrate the correct operation of the project, the neural microprocessor is simulated and then tested on the FPGA of a Nexys 4 development board, with the coprocessor implemented for solving the XOR problem. The coprocessor implementation is replicated with C and executed in the FPGA using only the default processor without being modified. Finally, the results are analyzed and compared to determine the trade-offs between the two approaches in terms of execution time, power consumption, and utilized space

    CIRCUITS AND ARCHITECTURE FOR BIO-INSPIRED AI ACCELERATORS

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    Technological advances in microelectronics envisioned through Moore’s law have led to powerful processors that can handle complex and computationally intensive tasks. Nonetheless, these advancements through technology scaling have come at an unfavorable cost of significantly larger power consumption, which has posed challenges for data processing centers and computers at scale. Moreover, with the emergence of mobile computing platforms constrained by power and bandwidth for distributed computing, the necessity for more energy-efficient scalable local processing has become more significant. Unconventional Compute-in-Memory architectures such as the analog winner-takes-all associative-memory and the Charge-Injection Device processor have been proposed as alternatives. Unconventional charge-based computation has been employed for neural network accelerators in the past, where impressive energy efficiency per operation has been attained in 1-bit vector-vector multiplications, and in recent work, multi-bit vector-vector multiplications. In the latter, computation was carried out by counting quanta of charge at the thermal noise limit, using packets of about 1000 electrons. These systems are neither analog nor digital in the traditional sense but employ mixed-signal circuits to count the packets of charge and hence we call them Quasi-Digital. By amortizing the energy costs of the mixed-signal encoding/decoding over compute-vectors with many elements, high energy efficiencies can be achieved. In this dissertation, I present a design framework for AI accelerators using scalable compute-in-memory architectures. On the device level, two primitive elements are designed and characterized as target computational technologies: (i) a multilevel non-volatile cell and (ii) a pseudo Dynamic Random-Access Memory (pseudo-DRAM) bit-cell. At the level of circuit description, compute-in-memory crossbars and mixed-signal circuits were designed, allowing seamless connectivity to digital controllers. At the level of data representation, both binary and stochastic-unary coding are used to compute Vector-Vector Multiplications (VMMs) at the array level. Finally, on the architectural level, two AI accelerator for data-center processing and edge computing are discussed. Both designs are scalable multi-core Systems-on-Chip (SoCs), where vector-processor arrays are tiled on a 2-layer Network-on-Chip (NoC), enabling neighbor communication and flexible compute vs. memory trade-off. General purpose Arm/RISCV co-processors provide adequate bootstrapping and system-housekeeping and a high-speed interface fabric facilitates Input/Output to main memory

    Simulation and implementation of novel deep learning hardware architectures for resource constrained devices

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    Corey Lammie designed mixed signal memristive-complementary metal–oxide–semiconductor (CMOS) and field programmable gate arrays (FPGA) hardware architectures, which were used to reduce the power and resource requirements of Deep Learning (DL) systems; both during inference and training. Disruptive design methodologies, such as those explored in this thesis, can be used to facilitate the design of next-generation DL systems

    Power Converters in Power Electronics

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    In recent years, power converters have played an important role in power electronics technology for different applications, such as renewable energy systems, electric vehicles, pulsed power generation, and biomedical sciences. Power converters, in the realm of power electronics, are becoming essential for generating electrical power energy in various ways. This Special Issue focuses on the development of novel power converter topologies in power electronics. The topics of interest include, but are not limited to: Z-source converters; multilevel power converter topologies; switched-capacitor-based power converters; power converters for battery management systems; power converters in wireless power transfer techniques; the reliability of power conversion systems; and modulation techniques for advanced power converters
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