24 research outputs found
A Low-Power DSP Architecture for a Fully Implantable Cochlear Implant System-on-a-Chip.
The National Science Foundation Wireless Integrated Microsystems (WIMS) Engineering Research Center at the University of Michigan developed Systems-on-a-Chip to achieve biomedical implant and environmental monitoring functionality in low-milliwatt power consumption and 1-2 cm3 volume. The focus of this work is implantable electronics for cochlear implants (CIs), surgically implanted devices that utilize existing nerve connections between the brain and inner-ear in cases where degradation of the sensory hair cells in the cochlea has occurred. In the absence of functioning hair cells, a CI processes sound information and stimulates the nderlying nerve cells with currents from implanted electrodes, enabling the patient to understand speech.
As the brain of the WIMS CI, the WIMS microcontroller unit (MCU) delivers the communication, signal processing, and storage capabilities required to satisfy the aggressive goals set forth. The 16-bit MCU implements a custom instruction set architecture focusing on power-efficient execution by providing separate data and address register windows, multi-word arithmetic, eight addressing modes, and interrupt and subroutine support. Along with 32KB of on-chip SRAM, a low-power 512-byte scratchpad memory is utilized by the WIMS custom compiler to obtain an average of 18% energy savings across benchmarks. A synthesizable dynamic frequency scaling circuit allows the chip to select a precision on-chip LC or ring oscillator, and perform clock scaling to minimize power dissipation; it provides glitch-free, software-controlled frequency shifting in 100ns, and dissipates only 480ÎŒW.
A highly flexible and expandable 16-channel Continuous Interleaved Sampling Digital Signal Processor (DSP) is included as an MCU peripheral component. Modes are included to process data, stimulate through electrodes, and allow experimental stimulation or processing. The entire WIMS MCU occupies 9.18mm2 and consumes only 1.79mW from 1.2V in DSP mode. This is the lowest reported consumption for a cochlear DSP.
Design methodologies were analyzed and a new top-down design flow is presented that encourages hardware and software co-design as well as cross-domain verification early in the design process. An O(n) technique for energy-per-instruction estimations both pre- and post-silicon is presented that achieves less than 4% error across benchmarks.
This dissertation advances low-power system design while providing an improvement in hearing recovery devices.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91488/1/emarsman_1.pd
Closed-loop approaches for innovative neuroprostheses
The goal of this thesis is to study new ways to interact with the nervous system in case of damage or pathology. In particular, I focused my effort towards the development of innovative, closed-loop stimulation protocols in various scenarios: in vitro, ex vivo, in vivo
FPGA-based implementation of speech recognition for robocar control using MFCC
This research proposes a simulation of the logic series of speech recognition on the MFCC (Mel Frequency Spread Spectrum) based FPGA and Euclidean Distance to control the robotic car motion. The speech known would be used as a command to operate the robotic car. MFCC in this study was used in the feature extraction process, while Euclidean distance was applied in the feature classification process of each speech that later would be forwarded to the part of decision to give the control logic in robotic motor. The test that has been conducted showed that the logic series designed was precise here by measuring the Mel Frequency Warping and Power Cepstrum. With the achievement of logic design in this research proven with a comparison between the Matlab computation and Xilinx simulation, it enables to facilitate the researchers to continue its implementation to FPGA hardware
Analog Compressive Sensing for Multi-Channel Neural Recording: Modeling and Circuit Level Implementation
RĂSUMĂ
Dans cette thĂšse, nous prĂ©sentons la conception dâun implant dâenregistrement neuronal multicanaux avec un Ă©chantillonnage compressĂ© mis en oeuvre avec un procĂ©dĂ© de fabrication CMOS Ă 65 nm.
La rĂ©duction de la technologie aËecte Ă la baisse les paramĂštres des amplificateurs neuronaux couplĂ©s en AC, comme la frĂ©quence de coupure basse, en raison de lâeËet de canal court des transistors MOS.
Nous analysons la frĂ©quence de coupure basse et nous constatons que lâorigine de ce problĂšme, dans les technologies avancĂ©es, est la diminution de lâimpĂ©dance dâentrĂ©e de lâamplificateur opĂ©rationnel de transconductance (OTA) en raison de la fuite dâoxyde de grille Ă lâentrĂ©e des OTA. Nous proposons deux solutions pour rĂ©duire la frĂ©quence de coupure basse sans augmenter la valeur des condensateurs de rĂ©troaction de lâĂ©tage dâentrĂ©e. La premiĂšre solution est appelĂ©e rĂ©troaction positive croisĂ©e et la deuxiĂšme solution utilise des PMOS Ă oxyde Ă©pais dans la paire de lâentrĂ©e diËĂ©rentielle de lâOTA. Il est Ă noter que pour compresser le signal neuronal, nous utilisons le CS dans le domaine analogique.
Pour la rĂ©alisation, un intĂ©grateur Ă capacitĂ© commutĂ©e est requis. Les paramĂštres non idĂ©aux de lâOTA utilisĂ© dans cet intĂ©grateur, tels que le gain fini, la bande passante, la vitesse de balayage et le changement rapide de la sortie. Toutes ces imperfections induisent des erreurs et rĂ©duisent le rapport signal sur bruit (SNR) total. Nous avons simulĂ© ces imperfections sur Matlab et Simulink pour dĂ©finir les spĂ©cifications de lâOTA requis. Aussi, pour concevoir les circuits analogiques correspondant aux interfaces neuronales requises, tels quâun amplificateur neuronal, une rĂ©fĂ©rence de tension compacte et Ă faible consommation dâĂ©nergie est requise. Nous avons proposĂ© une rĂ©fĂ©rence de tension de faible consommation dâĂ©nergie sans utiliser le transistor bipolaire parasite de la technologie CMOS pour diminuer la surface de silicium requise. Finalement, nous avons complĂ©tĂ© lâencodeur de CS et un convertisseur analogique-numĂ©rique Ă approximation successive (SAR ADC) requis pour la chaine dâenregistrement des signaux neuronaux dans ce projet.----------ABSTRACT
In this thesis we present the design of a multi-channel neural recording implant with analog compressive sensing (CS) in 65 nm process.
Scaling down technology demotes the parameters of AC-coupled neural amplifiers, such as increasing the low-cutoË frequency due to the short-channel eËects of MOS transistors.
We analyze the low-cutoË frequency and find that the main reason of this problem in advanced technologies is decreasing the input resistance of the operational transconductance amplifier (OTA) due to the gate oxide static current leakage in the input of the OTA. In advanced technologies, the gate oxide is thin and some electrons can penetrate to the channel and cause DC current leakage. We proposed two solutions to reduce the low-cutoË frequency without increasing the value of the feedback capacitors of the front-end neural amplifier. The first solution is called cross-coupled positive feedback, and the second solution is utilizing thick-oxide PMOS transistors in the input diËerential pair of the OTA. Compress the neural signal, we utilized the CS method in analog domain.
For its implementation, a switched-capacitor integrator is required. Non-ideal specifications of OTA of CS integrator such as finite gain, bandwidth, slew rate and output swing induce error and reduce the total signal to noise ratio (SNR). We simulated these non-idealities in Matlab and Simulink and extracted the specification of the required OTA. Also, to design analog circuits such as neural amplifier a low power and compact voltage reference is required. We implemented a low-power band-gap reference without utilizing parasitic bipolar transis-tor to decrease the silicon area. At the end, we completed the CS encoder and successive approximation architecture analog-to-digital converter (SAR ADC)
Neural networks-on-chip for hybrid bio-electronic systems
PhD ThesisBy modelling the brains computation we can further our understanding
of its function and develop novel treatments for neurological disorders. The
brain is incredibly powerful and energy e cient, but its computation does
not t well with the traditional computer architecture developed over the
previous 70 years. Therefore, there is growing research focus in developing
alternative computing technologies to enhance our neural modelling capability,
with the expectation that the technology in itself will also bene t from
increased awareness of neural computational paradigms.
This thesis focuses upon developing a methodology to study the design
of neural computing systems, with an emphasis on studying systems suitable
for biomedical experiments. The methodology allows for the design to be
optimized according to the application. For example, di erent case studies
highlight how to reduce energy consumption, reduce silicon area, or to
increase network throughput.
High performance processing cores are presented for both Hodgkin-Huxley
and Izhikevich neurons incorporating novel design features. Further, a complete
energy/area model for a neural-network-on-chip is derived, which is
used in two exemplar case-studies: a cortical neural circuit to benchmark
typical system performance, illustrating how a 65,000 neuron network could
be processed in real-time within a 100mW power budget; and a scalable highperformance
processing platform for a cerebellar neural prosthesis. From
these case-studies, the contribution of network granularity towards optimal
neural-network-on-chip performance is explored
Biologically inspired methods in speech recognition and synthesis: closing the loop
Current state-of-the-art approaches to computational speech recognition and synthesis are based on statistical analyses of extremely large data sets. It is currently unknown how these methods relate to the methods that the human brain uses to perceive and produce speech. In this thesis, I present a conceptual model, Sermo, which describes some of the computations that the human brain uses to perceive and produce speech. I then implement three large-scale brain models that accomplish tasks theorized to be required by Sermo, drawing upon techniques in automatic speech recognition, articulatory speech synthesis, and computational neuroscience.
The first model extracts features from an audio signal by performing a frequency decomposition with an auditory periphery model, then decorrelating the information in that power spectrum with methods commonly used in audio and image compression. I show that the features produced by this model implemented with biologically plausible spiking neurons can be used to classify phones in pre-segmented speech with significantly better accuracy than the features typically used in automatic speech recognition systems. Additionally, I show that this model can be used to compare auditory periphery models in terms of their ability to support phone classification of pre-segmented speech.
The second model uses a symbol-like neural representation of a sequence of syllables to generate a trajectory of premotor commands that can be used to control an articulatory synthesizer. I show that the model can produce trajectories up to several seconds in length from a static syllable sequence representation that result in intelligible synthesized speech. The trajectories reflect the high temporal variability of human speech, and smoothly transition between successive syllables, even in rapid utterances.
The third model classifies syllables from a trajectory of premotor commands. I show that the model is able to classify syllables online despite high temporal variability, and can produce the same syllable representations used by the second model. These two models can be connected in future work in order to implement a closed-loop sensorimotor speech system.
Unlike current computational approaches, all three of these models are implemented with biologically plausible spiking neurons, which can be simulated with neuromorphic hardware, and can interface naturally with artificial cochleas. All models are shown to scale to the level of adult human vocabularies in terms of the neural resources required, though limitations on their performance as a result of scaling will be discussed
Biomimetic Based Applications
The interaction between cells, tissues and biomaterial surfaces are the highlights of the book "Biomimetic Based Applications". In this regard the effect of nanostructures and nanotopographies and their effect on the development of a new generation of biomaterials including advanced multifunctional scaffolds for tissue engineering are discussed. The 2 volumes contain articles that cover a wide spectrum of subject matter such as different aspects of the development of scaffolds and coatings with enhanced performance and bioactivity, including investigations of material surface-cell interactions