Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey

The advancement of manufacturing technologies has enabled the integration of more intellectual property (IP) cores on the same system-on-chip (SoC). Scalable and high throughput on-chip communication architecture has become a vital component in today's SoCs. Diverse technologies such as electrical, wireless, optical, and hybrid are available for on-chip communication with different architectures supporting them. Security of the on-chip communication is crucial because exploiting any vulnerability would be a goldmine for an attacker. In this survey, we provide a comprehensive review of threat models, attacks, and countermeasures over diverse on-chip communication technologies as well as sophisticated architectures.Comment: 41 pages, 24 figures, 4 table

Towards trustworthy computing on untrustworthy hardware

Historically, hardware was thought to be inherently secure and trusted due to its obscurity and the isolated nature of its design and manufacturing. In the last two decades, however, hardware trust and security have emerged as pressing issues. Modern day hardware is surrounded by threats manifested mainly in undesired modifications by untrusted parties in its supply chain, unauthorized and pirated selling, injected faults, and system and microarchitectural level attacks. These threats, if realized, are expected to push hardware to abnormal and unexpected behaviour causing real-life damage and significantly undermining our trust in the electronic and computing systems we use in our daily lives and in safety critical applications. A large number of detective and preventive countermeasures have been proposed in literature. It is a fact, however, that our knowledge of potential consequences to real-life threats to hardware trust is lacking given the limited number of real-life reports and the plethora of ways in which hardware trust could be undermined. With this in mind, run-time monitoring of hardware combined with active mitigation of attacks, referred to as trustworthy computing on untrustworthy hardware, is proposed as the last line of defence. This last line of defence allows us to face the issue of live hardware mistrust rather than turning a blind eye to it or being helpless once it occurs. This thesis proposes three different frameworks towards trustworthy computing on untrustworthy hardware. The presented frameworks are adaptable to different applications, independent of the design of the monitored elements, based on autonomous security elements, and are computationally lightweight. The first framework is concerned with explicit violations and breaches of trust at run-time, with an untrustworthy on-chip communication interconnect presented as a potential offender. The framework is based on the guiding principles of component guarding, data tagging, and event verification. The second framework targets hardware elements with inherently variable and unpredictable operational latency and proposes a machine-learning based characterization of these latencies to infer undesired latency extensions or denial of service attacks. The framework is implemented on a DDR3 DRAM after showing its vulnerability to obscured latency extension attacks. The third framework studies the possibility of the deployment of untrustworthy hardware elements in the analog front end, and the consequent integrity issues that might arise at the analog-digital boundary of system on chips. The framework uses machine learning methods and the unique temporal and arithmetic features of signals at this boundary to monitor their integrity and assess their trust level

Decompose and Conquer: Addressing Evasive Errors in Systems on Chip

Modern computer chips comprise many components, including microprocessor cores, memory modules, on-chip networks, and accelerators. Such system-on-chip (SoC) designs are deployed in a variety of computing devices: from internet-of-things, to smartphones, to personal computers, to data centers. In this dissertation, we discuss evasive errors in SoC designs and how these errors can be addressed efficiently. In particular, we focus on two types of errors: design bugs and permanent faults. Design bugs originate from the limited amount of time allowed for design verification and validation. Thus, they are often found in functional features that are rarely activated. Complete functional verification, which can eliminate design bugs, is extremely time-consuming, thus impractical in modern complex SoC designs. Permanent faults are caused by failures of fragile transistors in nano-scale semiconductor manufacturing processes. Indeed, weak transistors may wear out unexpectedly within the lifespan of the design. Hardware structures that reduce the occurrence of permanent faults incur significant silicon area or performance overheads, thus they are infeasible for most cost-sensitive SoC designs. To tackle and overcome these evasive errors efficiently, we propose to leverage the principle of decomposition to lower the complexity of the software analysis or the hardware structures involved. To this end, we present several decomposition techniques, specific to major SoC components. We first focus on microprocessor cores, by presenting a lightweight bug-masking analysis that decomposes a program into individual instructions to identify if a design bug would be masked by the program's execution. We then move to memory subsystems: there, we offer an efficient memory consistency testing framework to detect buggy memory-ordering behaviors, which decomposes the memory-ordering graph into small components based on incremental differences. We also propose a microarchitectural patching solution for memory subsystem bugs, which augments each core node with a small distributed programmable logic, instead of including a global patching module. In the context of on-chip networks, we propose two routing reconfiguration algorithms that bypass faulty network resources. The first computes short-term routes in a distributed fashion, localized to the fault region. The second decomposes application-aware routing computation into simple routing rules so to quickly find deadlock-free, application-optimized routes in a fault-ridden network. Finally, we consider general accelerator modules in SoC designs. When a system includes many accelerators, there are a variety of interactions among them that must be verified to catch buggy interactions. To this end, we decompose such inter-module communication into basic interaction elements, which can be reassembled into new, interesting tests. Overall, we show that the decomposition of complex software algorithms and hardware structures can significantly reduce overheads: up to three orders of magnitude in the bug-masking analysis and the application-aware routing, approximately 50 times in the routing reconfiguration latency, and 5 times on average in the memory-ordering graph checking. These overhead reductions come with losses in error coverage: 23% undetected bug-masking incidents, 39% non-patchable memory bugs, and occasionally we overlook rare patterns of multiple faults. In this dissertation, we discuss the ideas and their trade-offs, and present future research directions.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147637/1/doowon_1.pd

Interim research assessment 2003-2005 - Computer Science

This report primarily serves as a source of information for the 2007 Interim Research Assessment Committee for Computer Science at the three technical universities in the Netherlands. The report also provides information for others interested in our research activities

A dietary interventional study moderating fat intake in Saudi subjects with metabolic disease

The gut-derived bacteria, endotoxin (lipopolysaccharide), have been observed to be raised in patients with type 2 diabetes mellitus (T2DM) and cardiovascular diseases (CVD) which appears to represent a source of diet induced inflammation exacerbating metabolic disease. To further the current studies on endotoxin induced inflammation investigations examined a cohort of adult Saudi Arabian women with obesity/weight gain and or T2DM to ascertain (1) the impact of a post-prandial high SFA rich meal on systemic inflammation; (2) the direct effect of a 3 month diet intervention on cardiometabolic health (3) and assess how subtle changes in dietary interventions can impact on metabolic risk in different patient groups and what dietary components appear important. A total of 92 Saudi adult women with varying metabolic states [18 nondiabetic (ND) control subjects (Age 24.4±7.9 years; BMI 22.2±2.2 Kg/m2), 24 overweight-plus obese (overweight+) subjects (Age 32.0±7.8 years; BMI 28.5±1.5 Kg/m2) and 50 T2DM patients (Age 41.5±6.2 years; BMI 35.2±7.7 Kg/m2)] were recruited for this 3-month intervention study. Anthropometric data and fasting blood samples were taken at pre- and 3 months post-intervention with glucose, insulin, HOMA-IR, lipid profile and endotoxin measured. To establish whether a high-fat meal alters circulating endotoxin in different metabolic disease states, all subjects were given a high fat standardized meal (75g fat, 5g carbohydrate, 6g protein) after an overnight fast of 12–14 h. Blood samples were drawn via cannula at baseline (0 hour) and post-prandially (1, 2, 3, and 4 hours). For the dietary intervention, participants were prescribed a 500Kcal deficit energy diet less than their daily recommended dietary allowances. Targeted macronutrient composition was 20%-30% fat, <10% of saturated fatty acids, 50%-60% carbohydrates, 15%-20% protein and at least 15g of fibre per 1000 kcal. At baseline and with the exception of HDL-cholesterol, all anthropometric, glycemic parameters, lipid profile and endotoxin were significantly higher in the T2DM group. For the high fat challenge, the most notable changes were the postprandial increases in the triglycerides, insulin, HOMA-IR and endotoxin levels, and subsequent significant decrease in HDL-cholesterol in all groups (p<0.05). These same patterns of changes were observed after 3 months in the overweight+ and T2DM group. Endotoxin was found to be significantly and positively associated with total and LDL-cholesterol (p<0.05), modestly with triglycerides and inversely with HDL-cholesterol (p=NS). For the dietary intervention, significant improvements were noted in all anthropometric measures in the T2DM group and BMI in the overweight+ group (p<0.01). The noted weight loss was secondary to the significant decrease in carbohydrates, fats and total caloric intakes (p<0.05) which translated to a better cardiometabolic health in both groups noted clearly through lipid profile changes. Endotoxin was found to be inversely associated with fiber intake (p<0.05). Fiber intake was found to be positively associated with HDL-cholesterol (p<0.05), which appeared to be an important dietary component to be associated with health improvements. This current thesis expanded our knowledge and understanding on how a high fat oral challenge exacerbates cardiometabolic and inflammatory conditions (including endotoxemia) in Saudi Arabian women with different metabolic states, and how a 3-month caloric restriction may induce weight loss that leads to improved cardiometabolic health. Observations from the present thesis highlight strategies that may potentially be of clinical use in future dietary intervention studies in patients with T2DM and obesity in the Middle Eastern region