High-Power Microwave/ Radio-Frequency Components, Circuits, and Subsystems for Next-Generation Wireless Radio Front-Ends

As the wireless communication systems evolve toward the future generation, intelligence will be the main signature/trend, well known as the concepts of cognitive and software-defined radios which offer ultimate data transmission speed, spectrum access, and user capacity. During this evolution, the human society may experience another round of `information revolution\u27. However, one of the major bottlenecks of this promotion lies in hardware realization, since all the aforementioned intelligent systems are required to cover a broad frequency range to support multiple communication bands and dissimilar standards. As the essential part of the hardware, power amplifiers (PAs) capable of operating over a wide bandwidth have been identified as the key enabling technology. This dissertation focuses on novel methodologies for designing and realizing broadband high-power PAs, their integration with high-quality-factor (high-Q) tunable filters, and relevant investigations on the reliabilities of these tunable devices. It can be basically divided into three major parts: 1.Broadband High-Efficiency Power Amplifiers. Obtaining high PA efficiency over a wide bandwidth is very challenging, because of the difficulty of performing broadband multi-harmonic matching. However, high efficiency is the critical feature for high-performance PAs due to the ever-increasing demands for environmental friendliness, energy saving, and longer battery life. In this research, novel design methodologies of broad-band highly efficient PAs are proposed, including the first-ever mode-transferring PA theory, novel matching network topology, and wideband reconfigurable PA architecture. These techniques significantly advance the state-of-the-art in terms of bandwidth and efficiency. 2.Co-Design of PAs and High-Q Tunable Filters. When implementing the intelligent communication systems, the conventional approach based on independent RF design philosophy suffers from many inherent defects, since no global optimization is achieved leading to degraded overall performance. An attractive method to solve these difficulties is to co-design critical modules of the transceiver chain. This dissertation presents the first-ever co-design of PAs and tunable filters, in which the redundant inter-module matching is entirely eliminated, leading to minimized size & cost and maximized overall performance. The saved hardware resources can be further transferred to enhance system functionalities. Moreover, we also demonstrate that co-design of PAs and filters can lead to more functionalities/benefits for the wireless systems, e.g. efficient and linear amplification of dual-carrier (or multi-carrier) signals. 3.High-Power/Non-Linear Study on Tunable Devices. High-power limitation/power handling is an everlasting theme of tunable devices, as it determines the operational life and is the threshold for actual industrial applications. Under high-power operation, the high RF voltage can lead to failures like tuners\u27 mechanical deflections and gas discharge in the small air spacing of the cavity. These two mechanisms are studied independently with their instantaneous and long-term effects on the device performance. In addition, an anti-biased topology of electrostatic RF MEMS varactors and tunable filters is proposed and experimentally validated for reducing the non-linear effect induced by bias-noise. These investigations will enlighten the designers on how to avoid and/or minimize the non-ideal effects, eventually leading to longer life cycle and performance sustainability of the tunable devices

Adaptive Power Amplifiers for Modern Communication Systems with Diverse Operating Conditions

In this thesis, novel designs for adaptive power amplifiers, capable of maintaining excellent performance at dissimilar signal parameters, are presented. These designs result in electronically reconfigurable, single-ended and Doherty power amplifiers (DPA) that efficiently sustain functionality at different driving signal levels, highly varying time domain characteristics and wide-spread frequency bands. The foregoing three contexts represent those dictated by the diverse standards of modern communication systems. Firstly, two prototypes for a harmonically-tuned reconfigurable matching network using discrete radio frequency (RF) microelectromechanical systems (MEMS) switches and semiconductor varactors will be introduced. Following that is an explanation of how the varactor-based matching network was used to develop a high performance reconfigurable Class F-1 power amplifier. Afterwards, a systematic design procedure for realizing an electronically reconfigurable DPA capable of operating at arbitrary centre frequencies, average power levels and back-off efficiency enhancement power ranges is presented. Complete sets of closed-form equations are outlined which were used to build tunable matching networks that compensate for the deviation of the Doherty distributed elements under the desired deployment scenarios. Off-the-shelf RF MEMS switches are used to realize the reconfigurability of the adaptive Doherty amplifiers. Finally, based on the derived closed-form equations, a tri-band, monolithically integrated DPA was realized using the Canadian Photonics Fabrication Centre (CPFC®) GaN500 monolithic microwave integrated circuit (MMIC) process. Successful integration of high power, high performance RF MEMS switches within the MMIC process paved the way for the realization of the frequency-agile, integrated version of the adaptive Doherty amplifier

Dual-band and switched-band highly efficient power amplifiers

The Power Amplifier is the most challenging module of a wireless network to design and it is the highest power consumer. Lots of research has been dedicated to design highly efficient and linear power amplifiers. The high demand for wireless communication systems creates the requirement for multiband transmitters and receivers. Providing high efficiency for power amplifiers in multiband applications is even more challenging. The work presented in this thesis is focused on designing high efficiency frequency adaptive power amplifiers. Frequency adaptive power amplifiers are categorized in three groups: broadband, multi-band and switched-band power amplifiers. Two main design methodologies of frequency adaptive power amplifiers are proposed in this thesis. They are dual-band and switched-band power amplifiers. The advantages and limitations of their output performances are evaluated. The main goals in this thesis are achieving high efficiency and required output power over all working bands and maintaining consistent performance over the bandwidth. In the dual-band power amplifiers, the distributed matching network is designed without any switches. Both of the switched-band Class-E power amplifiers have switched shunt capacitor values. The results demonstrate the tradeoffs between achieving consistent high performance in each band and introducing losses and complexity in the switching design

Design of a Direct-Modulation Transmitter with Self-Optimizing Feedback and a Highly Linear, Highly Reconfigurable, Continuously-Tunable Active-RC Baseband Filter for Multiple Standards

This work consists of two main parts: i) Design and implementation of a compact current-reusing 2.4GHz direct-modulation transmitter with on-chip automatic tuning; ii) Design and implementation of a novel highly-reconfigurable, continuously tunable, power-adjustable Active-RC filter for multiple standards. The design, analysis, and experimental verification of a proposed self-calibrating, current reused 2.4GHz, direct-modulation transmitter are introduced. A stacked arrangement of the power amplifier/voltage-controlled oscillator is presented along with a novel LC-tank-tuning algorithm with a simple, low-cost, on-chip implementation. To transmit maximum power, the tuning loop ensures the PA's resonant tank is centered around the operating frequency, and the loop requires no ADC, DSP, or external signal generator. This work also details the proposed tuning-loop algorithm and examines the frequency-dependent nonlinear power-detector. The system was implemented in TSMC 0.18[mu]m CMOS, occupies 0.7 mm² (TX) + 0.1 mm² (self tuning), and was measured in a QFN48 package on FR4 PCB. Automatically adjusting the tank-tuning bits within their tuning range results in >4dB increase in output power. With the self-tuning circuit active, the transmitter delivers a measured output power of > 0dBm to a 100-[omega] differential load, and the system consumes 22.9 mA from a 2.2-V supply. A biquad design methodology and a baseband low-pass filter is presented for wireless and wireline applications with reconfigurable frequency response, selectable order (1st/3rd/5th), continuously tunable cutoff frequency (1MHz-20MHz) and adjustable power consumption (3mW-7.5mW). A discrete capacitor array coarsely tunes the low-pass filter, and a novel Continuous Impedance Multiplier (CIM) then finely tunes the filter. Resistive/capacitive networks select between the Chebyshev and Inverse Chebyshev approximation types. Also, a new stability metric for biquads, Minimum Acceptable Phase Margin (MAPM), is presented and discussed in the context of filter compensation and passband ripple considerations. Experimental results yield an IIP3 of 31.3dBm, a THD of -40dB at 447mV[subscript pk, diff] input signal amplitude, and a DR of 71.4dB. The filters tunable range covers frequencies from 1MHz to 20MHz. In Inverse Chebyshev mode, the filter achieves a passband group delay variation less than ±2:5%. The design is fabricated in 0.13[mu]m CMOS, occupies 1.53mm², and operates from a 1-V supply

Radio-frequency integrated-circuit design for CMOS single-chip UWB systems

Low cost, a high-integrated capability, and low-power consumption are the basic requirements for ultra wide band (UWB) system design in order for the system to be adopted in various commercial electronic devices in the near future. Thus, the highly integrated transceiver is trended to be manufactured by companies using the latest silicon based complimentary metal-oxide-silicon (CMOS) processes. In this dissertation, several new structural designs are proposed, which provide solutions for some crucial RF blocks in CMOS for UWB for commercial applications. In this dissertation, there is a discussion of the development, as well as an illustration, of a fully-integrated ultra-broadband transmit/receive (T/R) switch which uses nMOS transistors with deep n-well in a standard 0.18-μm CMOS process. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET’s parasitic capacitances in order to synthesize artificial transmission lines which result in low insertion loss over an extremely wide bandwidth. Within DC-10 GHz, 10-18 GHz, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0 and 2.5 dB and isolation between 32-60 dB, 25-32 dB, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. Further, there is a discussion and demonstration of a tunable Carrier-based Time-gated UWB transmitter in this dissertation which uses a broadband multiplier, a novel fully integrated single pole single throw (SPST) switch designed by the CMOS process, where a tunable instantaneous bandwidth from 500 MHz to 4 GHz is exhibited by adjusting the width of the base band impulses in time domain. The SPST switch utilizes the synthetic transmission line concept and multiple reflections technique in order to realize a flat insertion loss less than 1.5 dB from 3.1 GHz to 10.6 GHz and an extremely high isolation of more than 45 dB within this frequency range. A fully integrated complementary LC voltage control oscillator (VCO), designed with a tunable buffer, operates from 4.6 GHz to 5.9 GHz. The measurement results demonstrate that the integrated VCO has a very low phase noise of –117 dBc/ Hz at 1 MHz offset. The fully integrated VCO achieves a very high figure of merit (FOM) of 183.5 using standard CMOS process while consuming 4 mA DC current