Photoresist-free printing of amorphous silicon thin-film transistors

Conventional fabrication of amorphous silicon thin-film transistors (a-Si TFTs) requires patterning numerous photoresist layers, a subtractive process that is time consuming and expensive. This letter describes transistor fabrication by a photoresist-free approach in which polymer etch masks are letterpress printed from flexible polyimide stamps. Pattern registration is achieved through optical alignment since the printed masks are thin and optically transparent. This modified fabrication scheme produces transistor performance equivalent to conventionally fabricated a-Si TFTs. The ability to directly print etch masks onto nonhomogeneous substrates brings one step closer the realization of flexible, large-area, macroelectronic fabrication

Charge transport in nanoscale vertical organic semiconductor pillar devices

We report charge transport measurements in nanoscale vertical pillar structures incorporating ultrathin layers of the organic semiconductor poly(3-hexylthiophene)(P3HT). P3HT layers with thickness down to 5 nm are gently top-contacted using wedging transfer, yielding highly reproducible, robust nanoscale junctions carrying high current densities (up to $10^6$ A/m$^2$). Current-voltage data modeling demonstrates excellent hole injection. This work opens up the pathway towards nanoscale, ultrashort-channel organic transistors for high-frequency and high-current-density operation.Comment: 30 pages, 8 figures, 1 tabl

A transistor based sensing platform and a microfluidic chip for a scaled-up simulation of controlled drug release

The framework of my thesis are Biomedical (or Biological) Microelectromechanical Systems (BioMEMSs). Two fields in which this discipline is involved are sensors and fluidics. Functionalized organic materials are under investigation to be the means for target biological sensing, and sensors are evolving to be integrated in fluidics platforms in order to produce in the future new small portable diagnostic devices. On the other hand one of the challenges of micro and nanofluidic technology is the fabrication of drug release devices, in order to control the amount of drug present in an organism. In this thesis these two arguments are considered. First we will discuss the implementation of a process oriented to the fabrication of an hybrid Organic Field Effect Transistor (OFET) with sensing capabilities from the semiconductive layer. In the second part we will show the fabrication process of a silicon based structure for the scaled-up characterization of drugs in nanochannels for controlled drug release. The characterization will consider charged microspheres playing the role of drugs to be tracked with a microscope. We will highlight also the possibility of implementing the transistor related technology in nanofluidic systems for the electronic controlled drug release

Study of the effects of deuterium implantation upon the performance of thin-oxide CMOS devices

The use of ultra thin oxide films in modem semiconductor devices makes them increasingly susceptible to damage due to the hot carrier damage. Deuterium in place of hydrogen was introduced by ion implantation at the silicon oxide-silicon interface during fabrication to satisfy the dangling bonds. Deuterium was implanted at energies of 15, 25 and 35 keV and at a dose of 1x1014/cm2. Some of the wafers were subjected to N2O annealing following gate oxide growth. It was demonstrated that ion implantation is an effective means of introduction of deuterium. Deuterium implantation brings about a clear enhancement in gate oxide quality by improving the interface characteristics. N2O annealing further improves device performance. A reduction of electron traps with deutenum was also observed. A combination of deuterium implantation at 25 keV and a dose of 1x1015/cm2, followed by annealing in N2O was observed to have the most positive influence on device behavior. Concurrently, MEMS microheaters being fabricated for an integrated VOC sensor were also tested for their temperature response to an applied voltage. Different channel configurations and materials for the conducting film were compared and the best pattern for rapid heating was identified. Temperature rises of upto 390° C were obtained. The temperature responses after coating spin-on glass in the microchannels were also measured

Design, fabrication and characterization of the infrastructure for a two part non volatile RAM

The present trend is to be able to develop cheaper and more convenient methods to design and fabricate non volatile RAM that will lead to an alteration of the computer architecture itself This will help replace the DRAM, which the computers currently have in their memory. The proposed NVRAM is designed to overcome the common difficulties faced with the use of ferroelectric materials used in the fabrication of NVRAM. The new idea essentially consists of fabricating the circuitry component separately and the substrate component separately and binding the two with the help of a conducting material. Electrical properties such as contact resistance and elasticity of the conducting material are very important. The design, simulation and fabrication of the circuitry part were carried out which would help test the conducting material. The conducting materials could be conducting polymer or indium bump pads. In this work the indium bump pads were deposited on the circuitry component and patterned. A glass plate with a conducting tin oxide film was then flipped over the entire device to evaluate the effectiveness of the 128 X 128 indium bump pads. The results obtained were very promising for actual fabrication of NVRAM using this technique

Selective Dry Etch for Defining Ohmic Contacts for High Performance ZnO TFTs

Recently, gigahertz RF performance has been demonstrated in zinc oxide (ZnO) TFT. However, the need arises for sub-micron channel length (Lc) dimensions to extend these results into X-band frequency range of operation. This thesis is a pioneering effort identifying device access materials to be selectively etched to ZnO via plasma-assisted etch (PAE) to avoid processing limitations from traditional optical lithography channel definition methods. A subtractive etch process using CF4/O2 gas mixture was completed with various Ohmic contact materials to ZnO providing foundational research upon which nano-scale, high-frequency ZnO thin-film transistors (TFTs) could be fabricated. Molybdenum, tantalum, titanium tungsten 10-90, and tungsten metallic contact schemes to ZnO are investigated for their etch selectivities to ZnO and etch profiles. Tungsten displayed promising device scalability results with excellent aspect ratio and 200nm Lc. A new semiconductor-semiconductor contact interface to ZnO using nc-Si is initially reported with 15mA/mm current density and 18mS/mm transconductance. Nc-Si also displays promising scaling results through the subtractive etch process defined with e-beam lithography. Results included 157nm channel length, high aspect ratio, and high extrapolated current density of nearly 1A/mm at 100nm Lc and gate and drain voltages of 10V

\u3cem\u3eMaterials Integration and Device Fabrication of Active Matrix Thin Film Transistor Arrays for Intracellular Gene Delivery\u3c/em\u3e

Materials and process integration of a thin film transistor array for intra/extracellular probing are described in this study. A combinatorial rf magnetron sputter deposition technique was employed to investigate the electrical characteristics and micro-structural properties of molybdenum tungsten (MoW) high temperature electrodes as a function of the binary composition. In addition to the composition, the effect of substrate bias and temperature was investigated. The electrical resistivity of MoW samples deposited at room temperature with zero bias followed the typical Nordheim’s rule as a function of composition. The resistivity of samples deposited with substrate bias is uniformly lower and obeyed the rule of mixtures as a function of composition. The metastable β-W phase was not observed in the biased films even when deposited at room temperature. High resolution scanning electron microscopy revealed a more dense structure for the biased films, which correlated to the significantly lower film resistivity. In order to overcome deficiencies in sputtered silicon dioxide (SiO2) films the rf magnetron sputtering process was optimized by using a full factorial design of experiment (DOE). The optimized SiO2 film has a 5.7 MV/cm breakdown field and a 6.2 nm/min deposition rate at 10 W/cm2 RF power, 3 mTorr pressure, 300 °C substrate temperature, and 56 V substrate bias. Thin film transistors (TFTs) were also fabricated and characterized to show the prospective applications of the optimized SiO2 films. The effect that direct current (DC) substrate bias has on radio frequency (RF)-sputter-deposited amorphous silicon (a-Si) films was also investigated. The substrate bias produces a denser a-Si film with fewer defects compared to unbiased films. The reduced number of defects results in a higher resistivity because defect-mediated conduction paths are reduced. Thin film transistors (TFT) that were completely sputter-deposited were fabricated and characterized. The TFT with the biased a-Si film showed lower leakage (off-state) current, higher on/off current ratio, and higher transconductance (field effect mobility) than the TFT with the unbiased a-Si film. The crystallization properties of amorphous silicon (a-Si) thin film deposited by rf magnetron sputter deposition with substrate bias have been thoroughly characterized. The crystallization speed can be increased and the crystallization temperature can be drastically lowered relative to unbiased a-Si even though the stress state of biased a-Si film is highly compressive. The substrate bias enhances defect formation (vacancies, dislocations, stacking faults) via ion bombardment during the film growth, which effectively increases the driving force for crystallization of the films. The electrical and optical properties of sputter-deposited silicon nitride (SiNx) and n+ amorphous silicon (n+ a-Si) films as a function of substrate bias during sputter deposition were investigated. The breakdown voltage of sputter-deposited SiNx with 20 W (125 V) substrate bias is 7.65 MV/cm which is equivalent to that of plasma enhanced chemical vapor deposition (PECVD) SiNx films. The conductivity of n+ a-Si films are also enhanced by applying substrate bias during the sputter deposition. To verify the effect of substrate bias, amorphous silicon thin film transistors (TFTs) were fabricated with substrate biased thin films and compared their electrical properties with conventional sputter deposited TFTs. Lastly, electrochemical measurements were analyzed using gold and pyrrole solution to verify the active addressability of the TFT array fabricated by entirely by sputter deposited thin films below 200 °C temperature

OXIDATION OF SILICON - THE VLSI GATE DIELECTRIC

Silicon dominates the semiconductor industry for good reasons. One factor is the stable, easily formed, insulating oxide, which aids high performance and allows practical processing. How well can these virtues survive as new demands are made on integrity, on smallness of feature sizes and other dimensions, and on constraints on processing and manufacturing methods? These demands make it critical to identify, quantify and predict the key controlling growth and defect processes on an atomic scale.The combination of theory and novel experiments (isotope methods, electronic noise, spin resonance, pulsed laser atom probes and other desorption methods, and especially scanning tunnelling or atomic force microscopies) provide tools whose impact on models is just being appreciated. We discuss the current unified model for silicon oxidation, which goes beyond the traditional descriptions of kinetic and ellipsometric data by explicitly addressing the issues raised in isotope experiments. The framework is still the Deal-Grove model, which provides a phenomenology to describe the major regimes of behaviour, and gives a base from which the substantial deviations can be characterized. In this model, growth is limited by diffusion and interfacial reactions operating in series. The deviations from Deal-Grove are most significant for just those first tens of atomic layers of oxide which are critical for the ultra-thin oxide layers now demanded. Several features emerge as important. First is the role of stress and stress relaxation. Second is the nature of the oxide closest to the Si, both its defects and its differences from the amorphous stoichiometric oxide further out, whether in composition, in network topology, or otherwise. Thirdly, we must consider the charge states of both fixed and mobile species. In thin films with very different dielectric constants, image terms can be important; these terms affect interpretation of spectroscopies, the injection of oxidant species and relative defect stabilities. This has added importance now that P-b concentrations have been correlated with interfacial stress. This raises further issues about the perfection of the oxide random network and the incorporation of interstitial species like molecular oxygen.Finally, the roles of contamination, particles, metals, hydrocarbons etc are important, as is interface roughness. These features depend on pre-gate oxide cleaning and define the Si surface that is to be oxidized which may have an influence on the features listed above