496 research outputs found

    Rapid Prototyping for Evaluating Vehicular Communications

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    [Abstract] This Thesis details the different elements of a rapid prototyping system able to implement and evaluate vehicular communications fast, according to the continuously evolving requirements of the industry. The system is basically composed of a testbed and a channel emulator, which allow evaluating communication transceivers in realistic vehicular scenarios. Two different testbeds are introduced: a generic 2x2 system and a vehicular platform. The former is used to compare and study space-time block coding (STBC) transmissions at 2.4 GHz over different indoor channels. The latter makes use of software transceivers whose performance is evaluated when they work under artificial high-speed Rayleigh-fading scenarios. To show the capabilities of both platforms, three software transceivers have been developed following the specifications for the physical layers of the standards IEEE 802.11p, IEEE 802.11a and IEEE 802.16e (Mobile WiMAX). The present work details the different elements that make up each transceiver and indicates how to connect them to the rest of the system to perform evaluation measurements. Finally, single-antenna and multi-antenna performances are measured thanks to the design and implementation of three FPGA-based channel emulators that are able to recreate up to seven different vehicular scenarios that include urban canyons, suburban areas and highways[Resumo] A presente Tese detalla os elementos necesarios para constituir un sistema basado en prototipado rápido capaz de levar a cabo e avaliar comunicacións vehiculares. O hardware do sistema está composto básicamente por unha plataforma de probas (testbed) e un emulador de canal, os cales permiten avaliar o rendemento de transceptores inartiamicos recreando diferentes escenarios vehiculares. Inicialmente, este traballo céntrase na descripción do hardware do sistema, detallando a construcción e proba dunha plataforma multi-antena e un testebed vehicular. Estos sistemas permitiron, respectivamente, estudar o comportamento de códigos STBC (space-time block codes) en interiores e medir o rendemento de tranceptores software ao traballar a distintas velocidades vehiculares en canais con desvaecemento Rayleigh. Tres transceptores software foron creados seguindo as especificacións das capas físicas dos estándares IEEE 802.11p, IEEE 802.11a e IEEE 802.16e (Mobile WiMAX). Este traballo detalla os diferentes componentes de cada transceptor, indicando cómo conectalos ao resto do sistema para realizar a avaliacition do seu rendemento. Dita avaliación realizouse coa axuda de tres emuladores de canal basados en tecnoloxía FPGA (Field Programmable Gate Array), os cales son capaces de recrear ata sete escenarios vehiculares distintos, incluindo cañóns urbanos, zonas suburbanas e autopistas.[Resumen] La presente Tesis detalla los elementos necesarios para constituir un sistema basado en prototipado rtiapido capaz de llevar a cabo y evaluar comunicaciones vehiculares. El hardware del sistema está compuesto por una plataforma de pruebas (testbed) y un emulador de canal, los cuales permiten evaluar el rendimiento de transceptores inaltiambricos recreando diferentes escenarios vehiculares. Inicialmente, este trabajo se centra en la descripcition del hardware del sistema, detallando la construccition y prueba de una plataforma multi-antena y un testebed vehicular. Estos sistemas han permitido, respectivamente, estudiar el comportamiento de ctiodigos STBC (space-time block codes) en interiores y medir el rendimiento en canal con desvanecimiento Rayleigh de tranceptores software a distintas velocidades vehiculares. Tres transceptores software han sido creados siguiendo las especificaciones de las capas físicas de los estandares IEEE 802.11p, IEEE 802.11a e IEEE 802.16e (Mobile WiMAX). Este trabajo detalla los diferentes componentes de cada transceptor, indicando ctiomo conectarlos al resto del sistema para realizar la evaluacition de su rendimiento. Dicha evaluacition se realiztio con la ayuda de tres emuladores de canal basados en FPGAs (Field Programmable Gate Array), los cuales son capaces de recrear comunicaciones multi-antena en hasta siete escenarios vehiculares distintos, incluyendo cañones urbanos, zonas suburbanas y autopistas

    VLSI Architectures and Rapid Prototyping Testbeds for Wireless Systems

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    The rapid evolution of wireless access is creating an ever changing variety of standards for indoor and outdoor environments. The real-time processing demands of wireless data rates in excess of 100 Mbps is a challenging problem for architecture design and verification. In this paper, we consider current trends in VLSI architecture and in rapid prototyping testbeds to evaluate these systems. The key phases in multi-standard system design and prototyping include: Algorithm Mapping to Parallel Architectures – based on the real-time data and sampling rate and the resulting area, time and power complexity; Configurable Mappings and Design Exploration – based on heterogeneous architectures consisting of DSP, programmable application-specific instruction (ASIP) processors, and co-processors; and Verification and Testbed Integration – based on prototype implementation on programmable devices and integration with RF units.Nokia Foundation FellowshipNokia CorporationNational InstrumentsNational Science Foundatio

    Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using an HLS Methodology

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    Many very-high-complexity signal processing algorithms are required in future wireless systems, giving tremendous challenges to real-time implementations. In this paper, we present our industrial rapid prototyping experiences on 3G/4G wireless systems using advanced signal processing algorithms in MIMO-CDMA and MIMO-OFDM systems. Core system design issues are studied and advanced receiver algorithms suitable for implementation are proposed for synchronization, MIMO equalization, and detection. We then present VLSI-oriented complexity reduction schemes and demonstrate how to interact these high-complexity algorithms with an HLS-based methodology for extensive design space exploration. This is achieved by abstracting the main effort from hardware iterations to the algorithmic C/C++ fixed-point design. We also analyze the advantages and limitations of the methodology. Our industrial design experience demonstrates that it is possible to enable an extensive architectural analysis in a short-time frame using HLS methodology, which significantly shortens the time to market for wireless systems.National Science Foundatio

    A software definable MIMO testbed: architecture and functionality

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    Following the intensive theoretical studies of recently emerged MIMO technology, a variety of performance measures become important to investigate the challenges and trade-offs at various levels throughout MIMO system design process. This paper presents a review of the MIMO testbed recently set up at King’s College London. The architecture that distinguishes the testbed as a flexible and reconfigurable system is first preseneted. This includes both the hardware and software aspects, and is followed by a discussion of implementation methods and evaluation of system research capabilities

    Artificial Intelligence-aided OFDM Receiver: Design and Experimental Results

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    Orthogonal frequency division multiplexing (OFDM) is one of the key technologies that are widely applied in current communication systems. Recently, artificial intelligence (AI)-aided OFDM receivers have been brought to the forefront to break the bottleneck of the traditional OFDM systems. In this paper, we investigate two AI-aided OFDM receivers, data-driven fully connected-deep neural network (FC-DNN) receiver and model-driven ComNet receiver, respectively. We first study their performance under different channel models through simulation and then establish a real-time video transmission system using a 5G rapid prototyping (RaPro) system for over-the-air (OTA) test. To address the performance gap between the simulation and the OTA test caused by the discrepancy between the channel model for offline training and real environments, we develop a novel online training strategy, called SwitchNet receiver. The SwitchNet receiver is with a flexible and extendable architecture and can adapts to real channel by training one parameter online. The OTA test verifies its feasibility and robustness to real environments and indicates its potential for future communications systems. At the end of this paper, we discuss some challenges to inspire future research.Comment: 29 pages, 13 figures, submitted to IEEE Journal on Selected Areas in Communication

    Reconfigurable Architectures for Wireless Systems: Design Exploration and Integration Challenges

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    Mobile devices are severely power and area limited due to battery capacity and system size. In many of these example systems, advanced features require computationally complex signal processing on high-speed data streams for enhanced networking capabilities. Thus, mapping high-level communication and networking algorithms to system architectures is a complex and challenging procedure. An important challenge is to characterize the area, time, and power requirements of these embedded system modules and to use this information effectively to determine the architecture of programmable, reconfigurable, and fixed-function modules. In this paper, we will focus on application examples in wireless networking which highlight these challenges in reconfigurable systems integration.Nokia CorporationTexas Instruments IncorporatedNational Science Foundatio
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