Virtual Prototyping for Dynamically Reconfigurable Architectures using Dynamic Generic Mapping

This paper presents a virtual prototyping methodology for Dynamically Reconfigurable (DR) FPGAs. The methodology is based around a library of VHDL image processing components and allows the rapid prototyping and algorithmic development of low-level image processing systems. For the effective modelling of dynamically reconfigurable designs a new technique named, Dynamic Generic Mapping is introduced. This method allows efficient representation of dynamic reconfiguration without needing any additional components to model the reconfiguration process. This gives the designer more flexibility in modelling dynamic configurations than other methodologies. Models created using this technique can then be simulated and targeted to a specific technology using the same code. This technique is demonstrated through the realisation of modules for a motion tracking system targeted to a DR environment, RIFLE-62

A HT3 Platform for Rapid Prototyping and High Performance Reconfigurable Computing

FPGAs as reconfigurable devices play an important role in both rapid prototyping and high performance reconfigurable computing. Usually, FPGA vendors help the users with pre-designed cores, for instance for various communication protocols. However, this is only true for widely used protocols. In the use case described here, the target application may benefit from a tight integration of the FPGA in a computing system. Typical commodity protocols like PCI Express may not fulfill these demands. HyperTransport (HT), on the other hand, allows connecting directly and without intermediate bridges or protocol conversion to a processor interface. As a result, communication costs between the FPGA unit and both processor and main memory are minimal. In this paper we present an HT3 interface for Stratix IV based FPGAs, which allows for minimal latencies and high bandwidths between processor and device and main memory and device. Designs targeting a HT connection can now be prototyped in real world systems. Furthermore, this design can be leveraged for acceleration tasks, with the minimal communication costs allowing fine-grain work deployment and the use of cost-efficient main memory instead of size-limited and costly on-device memory

Special Session on Industry 4.0

No abstract available

Initial thoughts on rapid prototyping techniques

This paper sets some context, raises issues, and provides our initial thinking on the characteristics of effective rapid prototyping techniques.After discussing the role rapid prototyping techniques can play in the software lifecycle, the paper looks at possible technical approaches including: heavily parameterized models, reusable software, rapid prototyping languages, prefabrication techniques for system generation, and reconfigurable test harnesses.The paper concludes that a multi-faceted approach to rapid prototyping techniques is needed if we are to address a broad range of applications successfully -- no single technical approach suffices for all potentially desirable applications

GSFC Annual Scan Technology Review SpaceCube On-Board Processor Update

No abstract availabl

A general framework for efficient FPGA implementation of matrix product

Original article can be found at: http://www.medjcn.com/ Copyright Softmotor LimitedHigh performance systems are required by the developers for fast processing of computationally intensive applications. Reconfigurable hardware devices in the form of Filed-Programmable Gate Arrays (FPGAs) have been proposed as viable system building blocks in the construction of high performance systems at an economical price. Given the importance and the use of matrix algorithms in scientific computing applications, they seem ideal candidates to harness and exploit the advantages offered by FPGAs. In this paper, a system for matrix algorithm cores generation is described. The system provides a catalog of efficient user-customizable cores, designed for FPGA implementation, ranging in three different matrix algorithm categories: (i) matrix operations, (ii) matrix transforms and (iii) matrix decomposition. The generated core can be either a general purpose or a specific application core. The methodology used in the design and implementation of two specific image processing application cores is presented. The first core is a fully pipelined matrix multiplier for colour space conversion based on distributed arithmetic principles while the second one is a parallel floating-point matrix multiplier designed for 3D affine transformations.Peer reviewe

Reconfigurable Mobile Multimedia Systems

This paper discusses reconfigurability issues in lowpower hand-held multimedia systems, with particular emphasis on energy conservation. We claim that a radical new approach has to be taken in order to fulfill the requirements - in terms of processing power and energy consumption - of future mobile applications. A reconfigurable systems-architecture in combination with a QoS driven operating system is introduced that can deal with the inherent dynamics of a mobile system. We present the preliminary results of studies we have done on reconfiguration in hand-held mobile computers: by having reconfigurable media streams, by using reconfigurable processing modules and by migrating functions

An introduction of small-scale intelligent manufacturing system

Embargoed OA, manuscript version after 24 months from publishing date. Link to publishers version: http://doi.org/10.1109/SIMS.2016.7802896Manufacturing companies in Northern Peripheral and Arctic region are predominately small and medium-sized and face considerable challenges like geographical isolation and a lack of benefits offered by industrial clusters. For the ultimate goal of enhancing their competitiveness in a global market, it is imperative for companies to innovate or adopt innovations in order to quickly response to changes in market, meet customer demands, reduce time-to-market and lower cost. A novel concept for small-scale intelligent manufacturing systems (SIMS) is introduced, in which diverse methods and innovative technologies can be applied and integrated. This paper gives an introduction of SIMS, defines its design objectives, and summarizes major relevant tools, techniques and paradigms for the development of SIMS, to generate a facilitative environment for small and medium-scale manufacturing enterprises to embrace new and innovative technologies