Conference of Microelectronics Research 2001

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From Confrontation to Coopetition in the Globalized Semiconductor Industry

The silicon chip is not only a symbol of marvellous technologies that are transforming industrial production and leisure time in society, but also of trade and technology conflicts while at the same time offering the potential for cooperation.The purpose of this paper is to show that the semiconductor industry has moved from being highly confrontational to being much more cooperative as is evidenced by the emergence of cross-national strategic alliances between companies, spanning R&D, product development, production and distribution.Over the last 15 years the semiconductor industry has experienced startling reversals of competitive fortune in which the USA dominated in 1970s, then Japan entered in 1980s, and in 1986 surpassed the USA as the largest producer of semiconductors with most US firms abandoning DRAM production due to price competition.This reversal of market position has become known as the X-curve. Since the early 1990s the Americans are on top again but with the Koreans and the Taiwanese coming on fast.With China and perhaps India coming on line in the present decade or so, these reversals in competitiveness will continue to play themselves out in the market.Due to external economies and spillover effects for other industries, this industry is considered to be a strategic sector, not only in the USA, where the industry came into existence, but also in Japan and Europe.Observing the excessive returns earned initially in this industry in the USA, Japanese companies wanted to shift these profits, at least in part, to Japan, for which the Japanese government provided support.The closing of the Japanese market both to imports and foreign direct investment undermined the initial American competitive strength.In order to counteract the loss of competitiveness the US industry reacted, besides by restructuring, by creating, with government funding, the research consortium SEMATECH, while the American government responded by concluding since 1986 bilateral trade agreements with Japan in which Japan initially agreed to "voluntarily" restrict its exports of semiconductors and to "voluntarily" expand the imports of American chips.In the mid-1980s Europe was a marginal player in the global competitive battle and suffered dependence on the USA and Japan.This was a consequence of decisions taken by European firms but part also lies in the fragmentation of the European market and the policy pursued by

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Aerosol chemical composition at Cabouw, The Netherlands as observed in two intensive periods in May 2008 and March 2009

Observations of aerosol chemical composition in Cabauw, the Netherlands, are presented for two intensive measurement periods in May 2008 and March 2009. Sub-micron aerosol chemical composition was measured by an Aerodyne Aerosol Mass Spectrometer (AMS) and is compared to observations from aerosol size distribution measurements as well as composition measurements with a Monitor for AeRosol and GAses (MARGA) based instrument and a Thermal-Desorption Proton-Transfer-Reaction Mass-Spectrometer (TD-PTR-MS). An overview of the data is presented and the data quality is discussed. In May 2008 enhanced pollution was observed with organics contributing 40% to the PM1 mass. In contrast the observed average mass loading was lower in March 2009 and a dominance of ammonium nitrate (42%) was observed. The semi-volatile nature of ammonium nitrate is evident in the diurnal cycles with maximum concentrations observed in the morning hours in May 2008 and little diurnal variation observed in March 2009. Size dependent composition data from AMS measurements are presented and show a dominance of organics in the size range below 200 nm. A higher O:C ratio of the organics is observed for May 2008 than for March 2009. Together with the time series of individual tracer ions this shows the dominance of OOA over HOA in May 2008

OBSERVED NONLINEAR RESPONSES IN PATTERNED SUPERCONDUCTING, FERROMAGNETIC, AND INTERACTING THIN FILMS

Many advances in technology ranging from biology and medicine through engineering and computer science to fundamental physics and chemistry depend upon the capability to control the fabrication of materials and devices at the submicron scale. Quantum mechanical effects become increasingly important to atomic and molecular interactions as the distances between neighbors decrease. These effects will provide materials and device designers with additional flexibility to establish properties of the designers choice, but the cost of this additional flexibility must be paid in the complexity of nonlinearities entering the interactions and the design process. The work presented here has provided several early results on three such interactions among closely-spaced submicron material structures: 1) the properties of superconductivity have been studied, 2) the properties of ferromagnetism have been studied, and 3) the interactions between superconductivity and ferromagnetism have been studied. Since our work was published, there has been considerable interest in all three of these wide-open areas and hundreds or thousands of additional results are now in the literature. We have used standard methods from the semiconductor industry as well as innovative methods to fabricate micron and submicron devices for observation. Standard optical lithography and standard electron beam lithography have been implemented to shape micron and submicron structures, respectively. Additionally, a laser interferometric lithography method has been invented and used to shape submicron structures. The materials used were vanadium, niobium, nickel, and/or permalloy. We have utilized SQUID magnetometry and Hall effect magnetometry to observe the properties of superconductor structures and superconductorferromagnetic mixed systems. We have used SQUID magnetometry and ferromagnetic resonance to observe the physical properties of ferromagnetic structures and the interactions between adjacent structures. Using these materials and methods we have discovered an unusual paramagnetic Meissner effect in thin Nb films that exists at igh-applied magnetic fields. We have discovered fluxoid matching anomalies at low sample temperature. And we have discovered interactions between electron exchange and magnetic dipole forces. Additionally, we have found clear evidence to support several past hypotheses advanced by other authors

Production accompanying testing of the ATLAS Pixel module

The ATLAS Pixel detector, innermost sub-detector of the ATLAS experiment at LHC, CERN, can be sensibly tested in its entirety the first time after its installation in 2006. Because of the poor accessibility (probably once per year) of the Pixel detector and tight scheduling the replacement of damaged modules after integration as well as during operation will become a highly exposed business. Therefore and to ensure that no affected parts will be used in following production steps, it is necessary that each production step is accompanied by testing the components before assembly and make sure the operativeness afterwards. Probably 300 of about total 2000 semiconductor hybrid pixel detector modules will be build at the Universität Dortmund. Thus a production test setup has been build up and examined before starting serial production. These tests contain the characterization and inspection of the module components and the module itself under different environmental conditions and diverse operating parameters. Once a module is assembled the operativeness is tested with a radioactive source and the long-time stability is assured by a burn-in. A fully electrical characterization is the basis for module selection and sorting for the ATLAS Pixel detector. Additionally the charge collection behavior of irradiated and non irradiated modules has been investigated in the H8 beamline with 180 GeV pions