Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Energy efficient hybrid computing systems using spin devices

Emerging spin-devices like magnetic tunnel junctions (MTJ\u27s), spin-valves and domain wall magnets (DWM) have opened new avenues for spin-based logic design. This work explored potential computing applications which can exploit such devices for higher energy-efficiency and performance. The proposed applications involve hybrid design schemes, where charge-based devices supplement the spin-devices, to gain large benefits at the system level. As an example, lateral spin valves (LSV) involve switching of nanomagnets using spin-polarized current injection through a metallic channel such as Cu. Such spin-torque based devices possess several interesting properties that can be exploited for ultra-low power computation. Analog characteristic of spin current facilitate non-Boolean computation like majority evaluation that can be used to model a neuron. The magneto-metallic neurons can operate at ultra-low terminal voltage of ∼20mV, thereby resulting in small computation power. Moreover, since nano-magnets inherently act as memory elements, these devices can facilitate integration of logic and memory in interesting ways. The spin based neurons can be integrated with CMOS and other emerging devices leading to different classes of neuromorphic/non-Von-Neumann architectures. The spin-based designs involve `mixed-mode\u27 processing and hence can provide very compact and ultra-low energy solutions for complex computation blocks, both digital as well as analog. Such low-power, hybrid designs can be suitable for various data processing applications like cognitive computing, associative memory, and currentmode on-chip global interconnects. Simulation results for these applications based on device-circuit co-simulation framework predict more than ∼100x improvement in computation energy as compared to state of the art CMOS design, for optimal spin-device parameters

Proposed 10-bit High-speed Two-Step Neural-based Analog-to-Digital Converter

Two-step flash architectures are an effective means of realizing high speed, high resolution A/D converters. With conversion rates approaching half those of fully parallel A/D converter's, this type of architecture provides a relatively small input capacitance together with low power dissipation due to the reduced number of comparators required to achieve the high resolution. A two-'step architecture uses a sample and hold circuit together with a high speed NO � D/A coarse quantizer subtraction circuit. As a part of the effort it was determined that the sample and hold circuit requires a 1590 GHz process bandwidth for 10-bit 2.5GHz application. Such a bigh-performance sample and hold function is clearly not feasible with existing CMOS technology and is beyond the scope of this effort. The folding and interpolation architecture, successfully used in high speed and high resolution bipolar A/D converter [1][4], employs considerable fewer comparators than a fully parallel converter and in addition does not require a sample and hold. The result is a high speed, low power dissipation converter with small die area. While incorporating the folding and interpolation scheme with MOS devices, this type converter suffers from an inherent limitation associated with the linearity of velocity saturated MOS devices. The folding factor number is as small as two due to the soft non-linearity of MOSFET differential pair transfer function (see Appendix A). This restriction results in folding CMOS architecture have a large number of comparators and large power consumption as well as matching difficulties. It was also found that the required 2.5GHz bandwidth for a folding architecture with MOS devices is also well beyond the reach of any current process. Neural networks behave essentially like analog nonlinear circuits. Interconnections between neurons (the elementary processing units) permits one to obtain high parallel computational capabilities, which potentially ensure high speed conversion. The Hopfield neural network is one ofthe most popular networks for electronic neural computing due to the simplicity ofthe network architecture and quick convergence in the time domain. Hopfield neural-based NO converters have several advantages over conventional NO converters. For a 10 bit Hopfield A/D converter only 45 neurons and 10 voltage to current converters are required. Thus, this architecture has a significantly smaller area than the fully flash A/D converter which employs 1023 comparators in the 10 bit case. By adjusting the contribution values between the amplifiers with a learning rule, the adaptive A/D converter with linear A/D conversion performance can be made. The adaptability of a neural-based A/D converter can be useful to compensate for initial device mismatches or long-term characteristic drifts. However, the conversion rate performance is constrained by the worst case delay of LSB (Least Significant Bit) when neural-based architecture applies to 8 - 10 bit resolution. The worst case delay happens when the variation of input signal causes the digital output to be changed from 100 ...00 to 011 ... 11, or from 011 ... 11 to 100... 00. Moreover, the great size differences (up to 64 - 256) between neurons used in 8 - 10 bit application makes their matching very difficult to meet the resolution requirements. Therefore, the neural-based converter is suitable for the 4 - 5 bit resolution application and as previously noted has many advantages over the 4-5 bit flash NO converter

Time-domain optimization of amplifiers based on distributed genetic algorithms

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer EngineeringThe work presented in this thesis addresses the task of circuit optimization, helping the designer facing the high performance and high efficiency circuits demands of the market and technology evolution. A novel framework is introduced, based on time-domain analysis, genetic algorithm optimization, and distributed processing. The time-domain optimization methodology is based on the step response of the amplifier. The main advantage of this new time-domain methodology is that, when a given settling-error is reached within the desired settling-time, it is automatically guaranteed that the amplifier has enough open-loop gain, AOL, output-swing (OS), slew-rate (SR), closed loop bandwidth and closed loop stability. Thus, this simplification of the circuit‟s evaluation helps the optimization process to converge faster. The method used to calculate the step response expression of the circuit is based on the inverse Laplace transform applied to the transfer function, symbolically, multiplied by 1/s (which represents the unity input step). Furthermore, may be applied to transfer functions of circuits with unlimited number of zeros/poles, without approximation in order to keep accuracy. Thus, complex circuit, with several design/optimization degrees of freedom can also be considered. The expression of the step response, from the proposed methodology, is based on the DC bias operating point of the devices of the circuit. For this, complex and accurate device models (e.g. BSIM3v3) are integrated. During the optimization process, the time-domain evaluation of the amplifier is used by the genetic algorithm, in the classification of the genetic individuals. The time-domain evaluator is integrated into the developed optimization platform, as independent library, coded using C programming language. The genetic algorithms have demonstrated to be a good approach for optimization since they are flexible and independent from the optimization-objective. Different levels of abstraction can be optimized either system level or circuit level. Optimization of any new block is basically carried-out by simply providing additional configuration files, e.g. chromosome format, in text format; and the circuit library where the fitness value of each individual of the genetic algorithm is computed. Distributed processing is also employed to address the increasing processing time demanded by the complex circuit analysis, and the accurate models of the circuit devices. The communication by remote processing nodes is based on Message Passing interface (MPI). It is demonstrated that the distributed processing reduced the optimization run-time by more than one order of magnitude. Platform assessment is carried by several examples of two-stage amplifiers, which have been optimized and successfully used, embedded, in larger systems, such as data converters. A dedicated example of an inverter-based self-biased two-stage amplifier has been designed, laid-out and fabricated as a stand-alone circuit and experimentally evaluated. The measured results are a direct demonstration of the effectiveness of the proposed time-domain optimization methodology.Portuguese Foundation for the Science and Technology (FCT

A compact high-energy particle detector for low-cost deep space missions

Over the last few decades particle physics has led to many new discoveries, laying the foundation for modern science. However, there are still many unanswered questions which the next generation of particle detectors could address, potentially expanding our knowledge and understanding of the Universe. Owing to recent technological advancements, electronic sensors are now able to acquire measurements previously unobtainable, creating opportunities for new deep-space high-energy particle missions. Consequently, a new compact instrument was developed capable of detecting gamma rays, neutrons and charged particles. This instrument combines the latest in FPGA System-on-Chip technology as the central processor and a 3x3 array of silicon photomultipliers coupled with an organic plastic scintillator as the detector. Using modern digital pulse shape discrimination and signal processing techniques, the scintillator and photomultiplier combination has been shown to accurately discriminate between the di_erent particle types and provide information such as total energy and incident direction. The instrument demonstrated the ability to capture 30,000 particle events per second across 9 channels - around 15 times that of the U.S. based CLAS detector. Furthermore, the input signals are simultaneously sampled at a maximum rate of 5 GSPS across all channels with 14-bit resolution. Future developments will include FPGA-implemented digital signal processing as well as hardware design for small satellite based deep-space missions that can overcome radiation vulnerability

Digital signal processing and digital-to-analog converters for wide-band transmitters

In this thesis, the implementation methods of digital signal processing and digital-to-analog converters for wide-band transmitters are researched. With digital signal processing, the problems of analog signal processing, such as sensitivity to interference and nonidealities of the semiconductor processes, can be avoided. Also, the programmability can be implemented digitally more easily than by means of analog signal processing. During the past few years, wireless communications has evolved from analog to digital, and signal bandwidths have increased, enabling faster and faster data transmission. The evolution of semiconductor processes, decreasing linewidth and supply voltages, has decreased the size of the electronics and power dissipation, enabling the integration of larger and larger systems on single silicon chips. There is little overall benefit in decreasing linewidths to meet the needs of analog design, since it makes the design process more difficult as the device sizes cannot be scaled according to minimum linewidth and because of the decreasing supply voltage. On the other hand, the challenges of digital signal processing are related to the efficient realization of signal processing algorithms in such a way that the required area and power dissipation does not increase extensively. In this book, the problems related to digital filters, upconversion algorithms and digital-to-analog converters used in digital transmitters are researched. Research results are applied to the implementation of a transmitter for a third-generation WCDMA base-station. In addition, the theory of factors affecting the linearity and performance of digital-to-analog converters is researched, and a digital calibration algorithm for enhancement of the static linearity has been presented. The algorithm has been implemented together with a 16-bit converter; its functionality has been demonstrated with measurements.Tässä väitöskirjassa on tutkittu digitaalisen signaalinkäsittelyn toteuttamista ja digitaalisesta analogiseksi -muuntimia laajakaistaisiin lähettimiin. Digitaalisella signaalinkäsittelyllä voidaan välttää monia analogiseen signaalinkäsittelyyn liittyviä ongelmia, kuten häiriöherkkyyttä ja puolijohdeprosessien epäideaalisuuksien vaikutuksia. Myös ohjelmoitavuus on helpommin toteutettavissa digitaalisesti kuin analogisen signaalinkäsittelyn keinoin. Viime vuosina on langattomien tietoliikennejärjestelmien kehitys kulkenut analogisesta digitaaliseen, ja käytettävät signaalikaistanleveydet ovat kasvaneet mahdollistaen yhä nopeamman tiedonsiirron. Puolijohdeprosessien kehitys, kapeneva minimiviivanleveys ja pienemmät käyttöjännitteet, on pienentänyt elektroniikan kokoa ja tehonkulutusta mahdollistaen yhä suurempien kokonaisuuksien integroimisen yhdelle piisirulle. Viivanleveyksien pieneneminen ei kuitenkaan suoraan hyödytä analogiasuunnittelua, jossa piirielementtien kokoa ei välttämättä voida pienentää viivanleveyden pienentyessä, ja jossa madaltuva käyttöjännite ennemminkin hankaloittaa kuin helpottaa suunnittelua. Siksi yhä suurempi osa signaalinkäsittelystä pyritään tekemään digitaalisesti. Digitaalisen signaalinkäsittelyn ongelmat puolestaan liittyvät algoritmien tehokkaaseen toteuttamiseen siten, että piirien pinta-ala ja tehonkulutus eivät kasva liian suuriksi. Tässä kirjassa on tutkittu digitaalisessa lähettimessä tarvittavien digitaalisten suodattimien, ylössekoitusalgoritmien ja digitaalisesta analogiseksi -muuntimien toteuttamiseen liittyviä ongelmia. Tutkimustuloksia on sovellettu kolmannen sukupolven WCDMA-tukiasemalähettimen toteutuksessa. Lisäksi on tutkittu digitaalisesta analogiseksi -muuntimien lineaarisuuteen ja suorituskykyyn vaikuttavien seikkojen teoriaa, ja esitetty digitaalinen kalibrointialgoritmi muuntimen staattisen suorituskyvyn parantamiseksi. Algoritmi on toteutettu 16-bittisen muuntimen yhteydessä ja se on osoitettu toimivaksi mittauksin.reviewe

Double Resonant High-Frequency Converters for Wireless Power Transfer

This thesis describes novel techniques and developments in the design and implementation of a low power radio frequency (40kHz to 1MHz) wireless power transfer (WPT) system, with an application in the wireless charging of autonomous drones without physical connection to its on-board Battery Management System (BMS). The WPT system is developed around a matrix converter exploiting the benefits such as a small footprint (DC-link free), high efficiency and high power density. The overall WPT system topology discussed in this thesis is based on the current state-of-the-art found in literature, but enhancements are made through novel methods to further improve the converter’s stability, reduce control complexity and improve the wireless power efficiency. In this work, each part of the system is analysed and novel techniques are proposed to achieve improvements. The WPT system design methodology presented in this thesis commences with the use of a conventional full-bridge converter. For cost-efficiency and to improve the converters stability, a novel gate drive circuit is presented which provides self-generated negative bias such that a bipolar MOSFET drive can be driven without an additional voltage source or magnetic component. The switching control sequences for both a full-bridge and single phase to single phase matrix converter are analysed which show that the switching of a matrix converter can be considered to be the same as a full-bridge converter under certain conditions. A middleware is then presented that reduces the complexity of the control required for a matrix converter and enables control by a conventional full-bridge controller (i.e. linear controller or microcontroller). A novel technique that can maximise and maintain in real-time the WPT efficiency is presented using a maximum efficiency point tracking approach. A detailed study of potential issues that may affect the implementation of this novel approach are presented and new solutions are proposed. A novel wireless pseudo-synchronous sampling method is presented and implemented on a prototype system to realise the maximum efficiency point tracking approach. Finally, a new hybrid wireless phase-locked loop is presented and implemented to minimise the bandwidth requirements of the maximum efficiency point tracking approach. The performance and methods for implementation of the novel concepts introduced in this thesis are demonstrated through a number of prototypes that were built. These include a matrix converter and two full WPT systems with operating frequencies ranging from sub-megahertz to megahertz level. Moreover, the final prototype is applied to the charging of a quadcopter battery pack to successfully charge the pack wirelessly whilst actively balancing the cells. Hence, fast battery charging and cell balancing, which conventionally requires battery removal, can be achieved without re-balance the weight of the UAV

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within