Data Conversion Within Energy Constrained Environments

Within scientific research, engineering, and consumer electronics, there is a multitude of new discrete sensor-interfaced devices. Maintaining high accuracy in signal quantization while staying within the strict power-budget of these devices is a very challenging problem. Traditional paths to solving this problem include researching more energy-efficient digital topologies as well as digital scaling.;This work offers an alternative path to lower-energy expenditure in the quantization stage --- content-dependent sampling of a signal. Instead of sampling at a constant rate, this work explores techniques which allow sampling based upon features of the signal itself through the use of application-dependent analog processing. This work presents an asynchronous sampling paradigm, based off the use of floating-gate-enabled analog circuitry. The basis of this work is developed through the mathematical models necessary for asynchronous sampling, as well the SPICE-compatible models necessary for simulating floating-gate enabled analog circuitry. These base techniques and circuitry are then extended to systems and applications utilizing novel analog-to-digital converter topologies capable of leveraging the non-constant sampling rates for significant sample and power savings

Floating-Gate Design and Linearization for Reconfigurable Analog Signal Processing

Analog and mixed-signal integrated circuits have found a place in modern electronics design as a viable alternative to digital pre-processing. With metrics that boast high accuracy and low power consumption, analog pre-processing has opened the door to low-power state-monitoring systems when it is utilized in place of a power-hungry digital signal-processing stage. However, the complicated design process required by analog and mixed-signal systems has been a barrier to broader applications. The implementation of floating-gate transistors has begun to pave the way for a more reasonable approach to analog design. Floating-gate technology has widespread use in the digital domain. Analog and mixed-signal use of floating-gate transistors has only become a rising field of study in recent years. Analog floating gates allow for low-power implementation of mixed-signal systems, such as the field-programmable analog array, while simultaneously opening the door to complex signal-processing techniques. The field-programmable analog array, which leverages floating-gate technologies, is demonstrated as a reliable replacement to signal-processing tasks previously only solved by custom design. Living in an analog world demands the constant use and refinement of analog signal processing for the purpose of interfacing with digital systems. This work offers a comprehensive look at utilizing floating-gate transistors as the core element for analog signal-processing tasks. This work demonstrates the floating gate\u27s merit in large reconfigurable array-driven systems and in smaller-scale implementations, such as linearization techniques for oscillators and analog-to-digital converters. A study on analog floating-gate reliability is complemented with a temperature compensation scheme for implementing these systems in ever-changing, realistic environments

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Matrix Transform Imager Architecture for On-Chip Low-Power Image Processing

Camera-on-a-chip systems have tried to include carefully chosen signal processing units for better functionality, performance and also to broaden the applications they can be used for. Image processing sensors have been possible due advances in CMOS active pixel sensors (APS) and neuromorphic focal plane imagers. Some of the advantages of these systems are compact size, high speed and parallelism, low power dissipation, and dense system integration. One can envision using these chips for portable and inexpensive video cameras on hand-held devices like personal digital assistants (PDA) or cell-phones In neuromorphic modeling of the retina it would be very nice to have processing capabilities at the focal plane while retaining the density of typical APS imager designs. Unfortunately, these two goals have been mostly incompatible. We introduce our MAtrix Transform Imager Architecture (MATIA) that uses analog floating--gate devices to make it possible to have computational imagers with high pixel densities. The core imager performs computations at the pixel plane, but still has a fill-factor of 46 percent - comparable to the high fill-factors of APS imagers. The processing is performed continuously on the image via programmable matrix operations that can operate on the entire image or blocks within the image. The resulting data-flow architecture can directly perform all kinds of block matrix image transforms. Since the imager operates in the subthreshold region and thus has low power consumption, this architecture can be used as a low-power front end for any system that utilizes these computations. Various compression algorithms (e.g. JPEG), that use block matrix transforms, can be implemented using this architecture. Since MATIA can be used for gradient computations, cheap image tracking devices can be implemented using this architecture. Other applications of this architecture can range from stand-alone universal transform imager systems to systems that can compute stereoscopic depth.Ph.D.Committee Chair: Hasler, Paul; Committee Member: David Anderson; Committee Member: DeWeerth, Steve; Committee Member: Jackson, Joel; Committee Member: Smith, Mar

Quasi-Self-Powered Piezo-Floating-Gate Sensing Technology for Continuous Monitoring of Large-Scale Bridges

Developing a practical framework for long-term structural health monitoring (SHM) of large structures, such as a suspension bridge, poses several major challenges. The next generation of bridge SHM technology needs to continuously monitor conditions and issue early warnings prior to costly repair or catastrophic failures. Additionally, the technology has to interpret effects of rare, high-impact events like earthquakes or hurricanes. The development of this technology has become an even higher priority due to the fact that many of the world's bridges are reaching the end of their designed service lives. Current battery-powered wireless SHM methods use periodic sampling with relatively long sleep-cycles to increase a sensor's operational life. However, long sleep-cycles make the technology vulnerable to missing or misinterpreting the effect of a rare event. To address these practical issues, we present a novel quasi-self-powered sensing solution for long-term and cost-effective monitoring of large-scale bridges. The approach we propose combines our previously reported and validated self-powered Piezo-Floating-Gate (PFG) sensor in conjunction with an ultra-low-power, long-range wireless interface. The physics behind the PFG's operation enable it to continuously capture and store local, cumulative information regarding dynamic loading conditions of the bridge in non-volatile memory. Using extensive numerical and laboratory studies, we demonstrate the capabilities of the PFG sensor for predicting structural conditions. We then present a system level design that adapts PFG sensing for SHM in bridges. A challenging aspect of SHM in large-scale bridges is the need for long-range wireless interrogation, as many portions of the structure are not easily accessible for continual inspection and portions of the bridge cannot be frequently taken out-of-service. We show that by combining self-powered PFG sensors with a small battery and optimized long-range active wireless interface, we can realize a quasi-self-powered system that easily achieves a continuous operating lifespan in excess of 20 years. The efficiency and feasibility of the proposed method is verified in a case study of the Mackinac Bridge in Michigan, the longest suspension bridge across anchorages in the Western Hemisphere. Associated data from the deployment are discussed, in addition to limitations, challenges, and additional considerations for widespread field deployment of the proposed SHM framework

Design and Test of a Gate Driver with Variable Drive and Self-Test Capability Implemented in a Silicon Carbide CMOS Process

Discrete silicon carbide (SiC) power devices have long demonstrated abilities that outpace those of standard silicon (Si) parts. The improved physical characteristics allow for faster switching, lower on-resistance, and temperature performance. The capabilities unleashed by these devices allow for higher efficiency switch-mode converters as well as the advance of power electronics into new high-temperature regimes previously unimaginable with silicon devices. While SiC power devices have reached a relative level of maturity, recent work has pushed the temperature boundaries of control electronics further with silicon carbide integrated circuits. The primary requirement to ensure rapid switching of power MOSFETs was a gate drive buffer capable of taking a control signal and driving the MOSFET gate with high current required. In this work, the first integrated SiC CMOS gate driver was developed in a 1.2 μm SiC CMOS process to drive a SiC power MOSFET. The driver was designed for close integration inside a power module and exposure to high temperatures. The drive strength of the gate driver was controllable to allow for managing power MOSFET switching speed and potential drain voltage overshoot. Output transistor layouts were optimized using custom Python software in conjunction with existing design tool resources. A wafer-level test system was developed to identify yield issues in the gate driver output transistors. This method allowed for qualitative and quantitative evaluation of transistor leakage while the system was under probe. Wafer-level testing and results are presented. The gate driver was tested under high temperature operation up to 530 degrees celsius. An integrated module was built and tested to illustrate the capability of the gate driver to control a power MOSFET under load. The adjustable drive strength feature was successfully demonstrated

Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications