Simulation of Parallel Pipeline Radix 2^2 Architecture

In popular orthogonal frequency division multiplexing (OFDM) communication system processing is one of the key procedures Fast Fourier transform (FFT) and inversely for that Fast Fourier Transform (IFFT) is one of them. In this VLSI implementation Structured pipeline architectures, low power consumption, high speed and reduced chip area are the important concerns. In this paper, presentation of the worthy implementation of FFT/IFFT processor for OFDM applications is described. We obtain the single-path delay feedback architecture, to get a ROM of smaller size and this proposed architecture applies a reconfigurable complex multiplier. To minimize the error of truncation we apply a fixed width modified booth multiplier. As a result, the proposed radix-2k feed forward architectures even offer an attractive solution for current applications, and also open up a new research line on feed forward structures

The Fast Fourier Transform Algorithm and Its Application in Digital Image Processing

Transforms are new image processing tools that are being applied to a wide variety of image processing problems. Fourier Transform and similar frequency transform techniques are widely used in image understanding and image enhancement techniques. Fast Fourier Transform (FFT) is the variation of Fourier transform in which the computing complexity is largely reduced. FFT is a mathematical technique for transforming a time domain digital signal into a frequency domain representation of the relative amplitude of different regions in the signal. The objective of this paper is to develop FFT based image processing algorithm. FFT can be computed faster than the Discrete Fourier Transform (DFT) on the same machine. Key words: Fast Fourier Transform, Discrete Fourier Transform, Radix-2 FFT algorithm, Decimation in Time FFT, Time complexity

Design And Implementation Of Radix-4 Fast Fourier Transform In Asia Chip With 0.18 M Standard CMOS Technology [TK5102.9. S624 2008 f rb].

Jelmaan Fourier pantas (FFT) merupakan blok yang penting dan digunakan secara meluas dalam algoritma pemprosesan isyarat digital. The Fast Fourier Transform (FFT) is a critical block and widely used in digital signal processing algorithm

Direct split-radix algorithm for fast computation of type-II discrete Hartley transform

In this paper, a novel split-radix algorithm for fast calculation the discrete Hartley transform of type-II (DHT-II) is intoduced. The algorithm is established through the decimation in time (DIT) approach, and implementedby splitting a length N of DHT-II into one DHT-II of length N/2 for even-indexed samples and two DHTs-II of length N/4 for odd-indexed samples. The proposed algorithm possesses the desired properties such as regularity, inplace calculation and it is represented by simple closed form decomposition sleading to considerable reductions in the arithmetic complexity compared to the existing DHT-II algorithms. Additionally, the validity of the proposed algorithm has been confirmed through analysing the arithmetic complexityby calculating the number of real additions and multiplications and associating it with the existing DHT-II algorithms

New Decimation-In-Time Fast Hartley Transform Algorithm

This paper presents a new algorithm for fast calculation of the discrete Hartley transform (DHT) based on decimation-in-time (DIT) approach. The proposed radix-2^2 fast Hartley transform (FHT) DIT algorithm has a regular butterfly structure that provides flexibility of different powers-of-two transform lengths, substantially reducing the arithmetic complexity with simple bit reversing for ordering the output sequence. The algorithm is developed through the three-dimensional linear index map and by integrating two stages of the signal flow graph together into a single butterfly. The algorithm is implemented and its computational complexity has been analysed and compared with the existing FHT algorithms, showing that it is significantly reduce the structural complexity with a better indexing scheme that is suitable for efficient implementation

Type-II/III DCT/DST algorithms with reduced number of arithmetic operations

We present algorithms for the discrete cosine transform (DCT) and discrete sine transform (DST), of types II and III, that achieve a lower count of real multiplications and additions than previously published algorithms, without sacrificing numerical accuracy. Asymptotically, the operation count is reduced from ~ 2N log_2 N to ~ (17/9) N log_2 N for a power-of-two transform size N. Furthermore, we show that a further N multiplications may be saved by a certain rescaling of the inputs or outputs, generalizing a well-known technique for N=8 by Arai et al. These results are derived by considering the DCT to be a special case of a DFT of length 4N, with certain symmetries, and then pruning redundant operations from a recent improved fast Fourier transform algorithm (based on a recursive rescaling of the conjugate-pair split radix algorithm). The improved algorithms for DCT-III, DST-II, and DST-III follow immediately from the improved count for the DCT-II.Comment: 9 page