Guest editorial for the special issue on software-defined radio transceivers and circuits for 5G wireless communications

Yichuang Sun, Baoyong Chi, and Heng Zhang, Guest Editorial for the Special Issue on Software-Defined Radio Transceivers and Circuits for 5G Wireless Communications, published in IEEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 63 (1): 1-3, January 2016, doi: https://doi.org/10.1109/TCSII.2015.2506979.Peer reviewedFinal Accepted Versio

UMTV: a Single Chip TV Receiver for PDAs, PCs and Cell Phones

A zero-external-component TV receiver for portable platforms is realized in a mainstream 8GHz-f/sub t/ BiCMOS process. Die size is 5/spl times/5mm/sup 2/ and power dissipation is 50mA at 3V. The receiver includes a single tunable LNA (3mA) with less than 5dB NF from 40 to 900MHz. The programmable IF filters cover all analog and digital standards

Digitally-Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative “iterative” harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and 3.5 dBm in-band IIP3 while the out-of-band IIP3 is + 16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply

A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal processing libraries we have developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal processing systems, with correlators foremost among them,and facilitates upgrading to new generations of processing technology. We present several correlator deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes parameter application deployed on the Precision Array for Probing the Epoch of Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31 pages. v2: corrected typo, v3: corrected Fig. 1

Arquiteturas paralelas avançadas para transmissores 5G totalmente digitais

The fifth generation of mobile communications (5G) is being prepared and should be rolled out in the early coming years. Massive number of Radio-Frequency (RF) front-ends, peak data rates of 10 Gbps (everywhere and everytime), latencies lower than 10 msec and huge device densities are some of the expected disruptive capabilities. At the same time, previous generations can not be jeopardized, fostering the design of novel flexible and highly integrated radio transceivers able to support the simultaneous transmission of multi-band and multi-standard signals. The concept of all-digital transmission is being pointed out as a promising architecture to cope with such challenging requirements, due to its fully digital radio datapath. This thesis is focused on the proposal and validation of fully integrated and advanced digital transmitter architectures that excel the state-of-the-art in different figures of merit, such as transmission bandwidth, spectral purity, carrier agility, flexibility, and multi-band capability. The first part of this thesis introduces the concept of all-digital RF transmission. In particular, the foundations inherent to this thematic line are given, together with the recent advances reported in the state-of-the-art architectures.The core of this thesis, containing the main developments achieved during the Ph.D. work, is then presented and discussed. The first key contribution to the state-of-the-art is the use of cascaded Delta-Sigma (∆Σ) architectures to relax the analog filtering requirements of the conventional All-Digital Transmitters while maintaining the constant envelope waveform. Then, it is presented the first reported architecture where Antenna Arrays are directly driven by single-chip and single-bit All-Digital Transmitters, with promising results in terms of simplification of the RF front-ends and overall flexibility. Subsequently, the thesis proposes the first reported RF-stage All-Digital Transmitter that can be embedded within a single Field-Programmable Gate Array (FPGA) device. Thereupon, novel techniques to enable the design of wideband All-Digital Transmitters are reported. Finally, the design of concurrent multi-band transmitters is introduced. In particular, the design of agile and flexible dual and triple bands All-DigitalTransmitter (ADT) is demonstrated, which is a very important topic for scenarios that demand carrier aggregation. This Ph.D. contributes withseveral advances to the state-of-the-art of RF all-digital transmitters.A quinta geração de comunicações móveis (5G) está a ser preparada e deve ser comercializada nos próximos anos. Algumas das caracterı́sticas inovadoras esperadas passam pelo uso de um número massivo de font-ends de Rádio-Frequência (RF), taxas de pico de transmissão de dados de 10 Gbps (em todos os lugares e em todas as ocasiões), latências inferiores a 10 mseg e elevadas densidades de dispositivos. Ao mesmo tempo, as gerações anteriores não podem ser ignoradas, fomentando o design de novos transceptores de rádio flexı́veis e altamente integrados, capazes de suportar a transmissão simultânea de sinais multi-banda e multi-standard. O conceito de transmissão totalmente digital é considerado como um tipo de arquitetura promissora para lidar com esses requisitos desafiantes, devido ao seu datapath de rádio totalmente digital. Esta tese é focada na proposta e validação de arquiteturas de transmissores digitais totalmente integradas e avançadas que ultrapassam o estado da arte em diferentes figuras de mérito, como largura de banda de transmissão, pureza espectral, agilidade de portadora, flexibilidade e capacidade multibanda. A primeira parte desta tese introduz o conceito de transmissores de RF totalmente digitais. Em particular, os fundamentos inerentes a esta linha temática são apresentados, juntamente com os avanços mais recentes do estado-da-arte. O núcleo desta tese, contendo os principais desenvolvimentos alcançados durante o trabalho de doutoramento, é então apresentado e discutido. A primeira contribuição fundamental para o estado da arte é o uso de arquiteturas em cascata com moduladores ∆Σ para relaxar os requisitos de filtragem analógica dos transmissores RF totalmente digitais convencionais, mantendo a forma de onda envolvente constante. Em seguida, é apresentada a primeira arquitetura em que agregados de antenas são excitados diretamente por transmissores digitais de um único bit inseridos num único chip, com resultados promissores em termos de simplificação dos front-ends de RF e flexibilidade em geral. Posteriormente, é proposto o primeiro transmissor totalmente digital RF-stage relatado que pode ser incorporado dentro de um único Agregado de Células Lógicas Programáveis. Novas técnicas para permitir o desenho de transmissores RF totalmente digitais de banda larga são também apresentadas. Finalmente, o desenho de transmissores simultâneos de múltiplas bandas é exposto. Em particular, é demonstrado o desenho de transmissores de duas e três bandas ágeis e flexı́veis, que é um tópico essencial para cenários que exigem agregação de múltiplas bandas.Apoio financeiro da Fundação para a Ciência e Tecnologia (FCT) no âmbito de uma bolsa de doutoramento, ref. PD/BD/105857/2014.Programa Doutoral em Telecomunicaçõe

The FFX Correlator

We established a new algorithm for correlation process in radio astronomy. This scheme consists of the 1st-stage Fourier Transform as a filter and the 2nd-stage Fourier Transform for spectroscopy. The "FFX" correlator stands for Filter and FX architecture, since the 1st-stage Fourier Transform is performed as a digital filter, and the 2nd-stage Fourier Transform is performed as a conventional FX scheme. We developed the FFX correlator hardware not only for the verification of the FFX scheme algorithm but also for the application to the Atacama Submillimeter Telescope Experiment (ASTE) telescope toward high-dispersion and wideband radio observation at submillimeter wavelengths. In this paper, we present the principle of the FFX correlator and its properties, as well as the evaluation results with the production version.Comment: 20 figure