Radiation Hardening of Digital Color CMOS Camera-on-a-Chip Building Blocks for Multi-MGy Total Ionizing Dose Environments

The Total Ionizing Dose (TID) hardness of digital color Camera-on-a-Chip (CoC) building blocks is explored in the Multi-MGy range using 60Co gamma-ray irradiations. The performances of the following CoC subcomponents are studied: radiation hardened (RH) pixel and photodiode designs, RH readout chain, Color Filter Arrays (CFA) and column RH Analog-to-Digital Converters (ADC). Several radiation hardness improvements are reported (on the readout chain and on dark current). CFAs and ADCs degradations appear to be very weak at the maximum TID of 6 MGy(SiO2), 600 Mrad. In the end, this study demonstrates the feasibility of a MGy rad-hard CMOS color digital camera-on-a-chip, illustrated by a color image captured after 6 MGy(SiO2) with no obvious degradation. An original dark current reduction mechanism in irradiated CMOS Image Sensors is also reported and discussed

Radiation Tolerant Electronics, Volume II

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects

Development of the readout electronics for the high luminosity upgrade of the CMS outer strip tracker

The High-luminosity upgrade of the LHC will deliver the dramatic increase in luminosity required for precision measurements and to probe Beyond the Standard Model theories. At the same time, it will present unprecedented challenges in terms of pileup and radiation degradation. The CMS experiment is set for an extensive upgrade campaign, which includes the replacement of the current Tracker with another all-silicon detector with improved performance and reduced mass. One of the most ambitious aspects of the future Tracker will be the ability to identify high transverse momentum track candidates at every bunch crossing and with very low latency, in order to include tracking information at the L1 hardware trigger stage, a critical and effective step to achieve triggers with high purity and low threshold. This thesis presents the development and the testing of the CMS Binary Chip 2 (CBC2), a prototype Application Specific Integrated Circuit (ASIC) for the binary front-end readout of silicon strip detectors modules in the Outer Tracker, which also integrates the logic necessary to identify high transverse momentum candidates by correlating hits from two silicon strip detectors, separated by a few millimetres. The design exploits the relation between the transverse momentum and the curvature in the trajectory of charged particles subject to the large magnetic field of CMS. The logic which follows the analogue amplification and binary conversion rejects clusters wider than a programmable maximum number of adjacent strips, compensates for the geometrical offset in the alignment of the module, and correlates the hits between the two sensor layers. Data are stored in a memory buffer before being transferred to an additional buffer stage and being serially read-out upon receipt of a Level 1 trigger. The CBC2 has been subject to extensive testing since its production in January 2013: this work reports the results of electrical characterization, of the total ionizing dose irradiation tests, and the performance of a prototype module instrumented with CBC2 in realistic conditions in a beam test. The latter is the first experimental demonstration of the Pt-selection principle central to the future of CMS. Several total-ionizing-dose tests highlighted no functional issue, but observed significant excess static current for doses <1 Mrad. The source of the excess was traced to static leakage current in the memory pipeline, and is believed to be a consequence of the high instantaneous dose delivered by the x-ray setup. Nevertheless, a new SRAM layout aimed at removing the leakage path was proposed for the CBC3. The results of single event upset testing of the chip are also reported, two of the three distinct memory circuits used in the chip were proven to meet the expected robustness, while the third will be replaced in the next iteration of the chip. Finally, the next version of the ASIC is presented, highlighting the additional features of the final prototype, such as half-strip resolution, additional trigger logic functionality, longer trigger latency and higher rate, and fully synchronous stub readout.Open Acces

INTEGRATED CIRCUITS FOR HIGH ENERGY PHYSICS EXPERIMETNS

Integrated Circuits are used in most people\u2019s lives in the modern societies. An important branch of research and technology is focused on Integrated Circuit (IC) design, fabrication, and their efficient applications; moreover most of these activities are about commercial productions with applications in ambient environment. However the ICs play very important role in very advance research fields, as Astronomy or High Energy Physics experiments, with absolutely extreme environments which require very interdisciplinary research orientations and innovative solutions. For example, the Fast TracKer (FTK) electronic system, which is an important part of triggering system in ATLAS experiment at European Organization for Nuclear Research (CERN), in every second of experiment selects 200 interesting events among 40 millions of total events due to collision of accelerated protons. The FTK function is based on ICs which work as Content Addressable Memory (CAM). A CAM compares the income data with stored data and gives the addresses of matching data as an output. The amount of calculation in FTK system is out of capacity of commercial ICs even in very advanced technologies, therefore the development of innovative ICs is required. The high power consumption due to huge amount of calculation was an important limitation which is overcome by an innovative architecture of CAM in this dissertation. The environment of ICs application in astrophysics and High Energy Physics experiments is different from commercial ICs environment because of high amount of radiation. This fact started to get seriously attention after the first \u201cTelstar I\u201d satellite failure because of electronic damages due to radiation effects in space, and opened a new field of research mostly about radiation hard electronics. The multidisciplinary research in radiation hard electronic field is about radiation effects on semiconductors and ICs, deep understanding about the radiation in the extreme environments, finding alternative solutions to increase the radiation tolerance of electronic components, and development of new simulation method and test techniques. Chapter 2 of this dissertation is about the radiation effects on Silicon and ICs. Moreover, In this chapter, the terminologies of radiation effects on ICs are explained. In chapter 3, the space and high energy physics experiments environments, which are two main branches of radiation hard electronics research, are studied. The radiation tolerance in on-chip circuits is achieving by two kinds of methodology: Radiation Hardening By Process (RHBP) and Radiation Hardening By Design (RHBD). RHBP is achieved by changing the conventional fabrication process of commercial ICs. RHBP is very expensive so it is out of budget for academic research, and in most cases it is exclusive for military application, with very restricted rules which make the access of non-military organizations impossible. RHBD with conventional process is the approach of radiation hard IC design in this dissertation. RHBD at hardware level can be achieved in different ways: \u2022 System level RHBD: radiation hardening at system level is achieved by algorithms which are able to extract correct data using redundant information. \u2022Architecture level RHBD: some hardware architectures are able to prevent of lost data or mitigate the radiation effects on stored data without interfacing of software. Error Correction Code (ECC) circuits and Dual Interlocked storage CEll (DICE) architecture are two examples of RHBD at architecture level. \u2022 Circuit level RHBD: at circuit level, some structures are avoided or significantly reduced. For example, feedback loops with high gain are very sensitive to radiation effects. \u2022 Layout level RHBD: there are also different solutions in layout design level to increase the radiation tolerance of circuits. Specific shapes of transistor design, optimization of the physical distance between redundant data and efficient polarization of substrate are some techniques commonly used to increase significantly the radiation tolerance of ICs. An innovative radiation hard Static Random Access Memory (SRAM), designed in three versions, is presented in chapter 4. The radiation hardening is achieved by RHBD approach simultaneously at architecture, circuit and layout levels. Complementary Metal-Oxide-Semiconductor (CMOS) 65 nm is the technology of design and the prototype chip is fabricated at Taiwan Semiconductor Manufacturing Company (TSMC). Chapter 5 is about the development of simulation models that can help to predict the radiation effect in the behavior of SRAM block. The setup system developed to characterize the radiation hard SRAM prototype chip is presented in Chapter 5. The setup system gives the possibility of testing the prototype exposed under radiation in a vacuum chamberand regular laboratory environment. Chapter 6 is about the contribution of this dissertation on FTK project and the conclusion of all research activities is shown in the final part of this dissertation. The research activities of this dissertation in supported by Italian National Institute for Nuclear Physics (INFN) as part of CHIPIX65 project and RD53 collaboration at CERN

Electronic systems for intelligent particle tracking in the High Energy Physics field

This Ph.D thesis describes the development of a novel readout ASIC for hybrid pixel detector with intelligent particle tracking capabilities in High Energy Physics (HEP) application, called Macro Pixel ASIC (MPA). The concept of intelligent tracking is introduced for the upgrade of the particle tracking system of the Compact Muon Solenoid (CMS) experiment of the Large Hadron Collider (LHC) at CERN: this detector must be capable of selecting at front--end level the interesting particle and of providing them continuously to the back-end. This new functionality is required to cope with the improved performances of the LHC when, in about ten years' time, a major upgrade will lead to the High Luminosity scenario (HL-LHC). The high complexity of the digital logic for particle selection and the very low power requirement of 95% in particle selection and a data reduction from 200 Tb/s/cm2 to 1 Tb/s/cm2. A prototype, called MPA-Light, has been designed, produced and tested. According to the measurements, the prototype respects all the specications. The same device has been used for multi-chip assembly with a pixelated sensor. The assembly characterization with radioactive sources conrms the result obtained on the bare chip

Effects of Radiation on MEMS

The sensitivity of MEMS devices to radiation is reviewed, with an emphasis on radiation levels representative of space missions. While silicon and metals generally do not show mechanical degradation at the radiation levels encountered in most missions, MEMS devices have been reported to fail at doses of as few krad, corresponding to less than one year in most orbits. Radiation sensitivity is linked primarily to the impact on device operation of radiation-induced trapped charge in dielectrics, and thus affects most strongly MEMS devices operating on electrostatic principles. A survey of all published reports of radiation effects on MEMS is presented. The different sensing and actuation physical principles and materials used in MEMS are compared, leading to suggested was to increase radiation tolerance by design, for instance by choice of actuation principle or by electrical shielding of dielectrics

Power Management Circuits for Front-End ASICs Employed in High Energy Physics Applications

The instrumentation of radiation detectors for high energy physics calls for the development of very low-noise application-specific integrated-circuits and demanding system-level design strategies, with a particular focus on the minimisation of inter-ference noise from power anagement circuitry. On the other hand, the aggressive pixelisation of sensors and associated front-end electronics, and the high radiation exposure at the innermost tracking and vertex detectors, requires radiation-aware design and radiation-tolerant deep sub-micron CMOS technologies. This thesis explores circuit design techniques towards radiation tolerant power management integrated circuits, targeting applications on particle detectors and monitoring of accelerator-based experiments, aerospace and nuclear applications. It addresses advantages and caveats of commonly used radiation-hard layout techniques, which often employ Enclosed Layout or H-shaped transistors, in respect to the use of linear transistors. Radiation tolerant designs for bandgap circuits are discussed, and two different topologies were explored. A low quiescent current bandgap for sub-1 V CMOS circuits is proposed, where the use of diode-connected MOSFETs in weak-inversion is explored in order to increase its radiation tolerance. An any-load stable LDO architecture is proposed, and three versions of the design using different layout techniques were implemented and characterised. In addition, a switched DC-DC Buck converter is also studied. For reasons concerning testability and silicon area, the controller of the Buck converter is on-chip, while the inductance and the power transistors are left on-board. A prototype test chip with power management IP blocks was fabricated, using a TSMC 65 nm CMOS technology. The chip features Linear, ELT and H-shape LDO designs, bandgap circuits and a Buck DC-DC converter. We discuss the design, layout and test results of the prototype. The specifications in terms of voltage range and output current capability are based on the requirements set for the integrated on-detector electronics of the new CGEM-IT tracker for the BESIII detector. The thesis discusses the fundamental aspects of the proposed on-detector electronics and provides an in-depth depiction of the front-end design for the readout ASIC

Applications in Electronics Pervading Industry, Environment and Society

This book features the manuscripts accepted for the Special Issue “Applications in Electronics Pervading Industry, Environment and Society—Sensing Systems and Pervasive Intelligence” of the MDPI journal Sensors. Most of the papers come from a selection of the best papers of the 2019 edition of the “Applications in Electronics Pervading Industry, Environment and Society” (APPLEPIES) Conference, which was held in November 2019. All these papers have been significantly enhanced with novel experimental results. The papers give an overview of the trends in research and development activities concerning the pervasive application of electronics in industry, the environment, and society. The focus of these papers is on cyber physical systems (CPS), with research proposals for new sensor acquisition and ADC (analog to digital converter) methods, high-speed communication systems, cybersecurity, big data management, and data processing including emerging machine learning techniques. Physical implementation aspects are discussed as well as the trade-off found between functional performance and hardware/system costs

Performance evaluation of a fully depleted monolithic pixel detector chip in 150 nm CMOS technology

The depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a (fully) depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and highly resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, developed in a 150 nm process on a highly resistive n-type wafer of 50 µm thickness, were characterized. The prototypes have 352 square pixels of 40 µm pitch and a small n-well charge collection node with very low capacitance of 5 fF (n+-implantation size: 5 µm x 5 µm) and about 150 transistors per pixel (CSA and discriminator plus a small digital part). The characterization of the prototypes demonstrates the proof of principle of the concept. Prior to irradiation the prototypes show a signal from a minimum ionizing particle ranging from 2400 e- to 3000 e- while the noise is 30 e- due to the low capacitance. After the irradiation of the prototypes with neutrons up to a fluence of 5•1014 neutrons/cm2 the performance suffers from the radiation damage leading to a signal of 1000 e- and a higher noise of 60 e- due to the increase of the leakage current. The detection efficiency of the prototypes reduces from 94 % to 26 % after the fluence of 5•1014 particles/cm2. Due to the small fill factor the detection efficiency shows are strong dependence on the position within the pixel after irradiation. Thus the DMAPS concept with low fill factor can be used for precise vertex reconstruction in High Energy Physics experiments without severe performance loss up to moderate fluences (14 particles/cm2). The expected particle fluences inside of the volume of the upgrade of the ATLAS pixel detector exceed this limit. However, possible applications could be at future linear collider (ILC or CLIC) experiments and B-factories where the low material budget is of particular importance and the fluences are much less and X-ray imaging with low energy photons which would benefit from the good noise performance