A Novel Speculative Pseudo-Parallel \Delta\Sigma Modulator

We present a novel speculative pseudo-parallel \Delta\Sigma modulator structure, which almost halves the logic depth of the critical path in the pseudo-parallel Hatami structure. Following Hatami, our modulator calculates a block of n consecutive output bits in parallel, and then employs a parallelserial interface to output the bits at n times the modulator clock frequency. We circumvent the block-to-block dependence, which limits the clock speed of the Hatami structure, by speculatively calculating the outputs based on all possible output values of the previous block, and then selecting the correct one. We present cost and performance estimates for an initial implementation of the modulator, synthesized towards an FPGA and an ASIC technology

System level modelling and design of hypergraph based wireless system area networks for multi-computer systems

This thesis deals with issues pertaining the wireless multicomputer interconnection networks namely topology and Medium Access Control (MAC). It argues that new channel assignment technique based on regular low-dimensional hypergraph networks, the dual radio wireless hypermesh, represents a promising alternative high-performance wireless interconnection network for the future multicomputers to shared communication medium networks and/or ordinary wireless mesh networks, which have been widely used in current wireless networks. The focus of this work is on improving the network throughput while maintaining a relatively low latency of a wireless network system. By means of a Carrier Sense Multiple Access (CSMA) based design of the MAC protocol and based on the desirable features of hypermesh network topology a relatively high performance network has been introduced. Compared to the CSMA shared communication channel model, which is currently the de facto MAC protocol for most of wireless networks, our design is shown to achieve a significant increase in network throughput with less average network latency for large number of communication nodes. SystemC model of the proposed wireless hypermesh, validated through mathematical models, are then introduced. The analysis has been incorporated in the proper SystemC design methodology which facilitates the integration of communication modelling into the design modelling at the early stages of the system development. Another important application of SystemC modelling techniques is to perform meaningful comparative studies of different protocols, or new implementations to determine which communication scenario performs better and the ability to modify models to test system sensitivity and tune performance. Effects of different design parameters (e.g., packet sizes, number of nodes) has been carried out throughout this work. The results shows that the proposed structure has out perform the existing shared medium network structure and it can support relatively high number of wireless connected computers than conventional networks

Computationally Efficient Hybrid Interpolation and Baseline Restoration of the Brain-PET Pulses

The design and component level architectures of a novel offset compensated digital baseline restorer (BLR) and an original hybrid interpolator are described. It allows diminishing the effect of modifications occurring during the readout of Positron Emission Tomography (PET) pulses. Without treatment, such artifacts can result in a reduction in the scanner’s performance, such as its sensitivity and resolution. The BLR recompenses the offset of PET pulses. Afterward, the pertinent parts of these pulses are located. Onward, the located portion of the signal is resampled by using a hybrid interpolator. This is constructed by cascading an optimized weighted least-square interpolator (WLSI) and a Simplified Linear Interpolator (SLI). The regulation processes for the WLSI coefficients and evaluation of the BLR and the interpolator modules are presented. The proposed hybrid interpolator’s computational complexity is compared with classic counterparts. These modules are implemented in Very High-Speed Integrated Circuits Hardware Description Language (VHDL) and synthesized on a Field Programmable Gate Array (FPGA). The functionality of the system is validated with an experimental setup. Results reveal notable computational gain along with adequate dynamic restitution of the bipolar offsets besides a useful and accurate improvement of the temporal resolution relative to the computationally complex conventional equivalents

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

n/

Energy analysis and optimisation techniques for automatically synthesised coprocessors

The primary outcome of this research project is the development of a methodology enabling fast automated early-stage power and energy analysis of configurable processors for system-on-chip platforms. Such capability is essential to the process of selecting energy efficient processors during design-space exploration, when potential savings are highest. This has been achieved by developing dynamic and static energy consumption models for the constituent blocks within the processors. Several optimisations have been identified, specifically targeting the most significant blocks in terms of energy consumption. Instruction encoding mechanism reduces both the energy and area requirements of the instruction cache; modifications to the multiplier unit reduce energy consumption during inactive cycles. Both techniques are demonstrated to offer substantial energy savings. The aforementioned techniques have undergone detailed evaluation and, based on the positive outcomes obtained, have been incorporated into Cascade, a system-on-chip coprocessor synthesis tool developed by Critical Blue, to provide automated analysis and optimisation of processor energy requirements. This thesis details the process of identifying and examining each method, along with the results obtained. Finally, a case study demonstrates the benefits of the developed functionality, from the perspective of someone using Cascade to automate the creation of an energy-efficient configurable processor for system-on-chip platforms