192 research outputs found

    Power Reductions with Energy Recovery Using Resonant Topologies

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    The problem of power densities in system-on-chips (SoCs) and processors has become more exacerbated recently, resulting in high cooling costs and reliability issues. One of the largest components of power consumption is the low skew clock distribution network (CDN), driving large load capacitance. This can consume as much as 70% of the total dynamic power that is lost as heat, needing elaborate sensing and cooling mechanisms. To mitigate this, resonant clocking has been utilized in several applications over the past decade. An improved energy recovering reconfigurable generalized series resonance (GSR) solution with all the critical support circuitry is developed in this work. This LC resonant clock driver is shown to save about 50% driver power (\u3e40% overall), on a 22nm process node and has 50% less skew than a non-resonant driver at 2GHz. It can operate down to 0.2GHz to support other energy savings techniques like dynamic voltage and frequency scaling (DVFS). As an example, GSR can be configured for the simpler pulse series resonance (PSR) operation to enable further power saving for double data rate (DDR) applications, by using de-skewing latches instead of flip-flop banks. A PSR based subsystem for 40% savings in clocking power with 40% driver active area reduction xii is demonstrated. This new resonant driver generates tracking pulses at each transition of clock for dual edge operation across DVFS. PSR clocking is designed to drive explicit-pulsed latches with negative setup time. Simulations using 45nm IBM/PTM device and interconnect technology models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking. DVFS range from 2GHz/1.3V to 200MHz/0.5V is obtained. The PSR frequency is set \u3e3Ă— the clock rate, needing only 1/10th the inductance of prior-art LC resonance schemes. The skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times. Applications in data circuits are shown as well with a 90nm example. Parallel resonant and split-driver non-resonant configurations as well are derived from GSR. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared for the first time and verified. This enables synthesis of an optimal topology for a given application from the GSR

    Network-on-Chip

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    Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

    DFM Techniques for the Detection and Mitigation of Hotspots in Nanometer Technology

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    With the continuous scaling down of dimensions in advanced technology nodes, process variations are getting worse for each new node. Process variations have a large influence on the quality and yield of the designed and manufactured circuits. There is a growing need for fast and efficient techniques to characterize and mitigate the effects of different sources of process variations on the design's performance and yield. In this thesis we have studied the various sources of systematic process variations and their effects on the circuit, and the various methodologies to combat systematic process variation in the design space. We developed abstract and accurate process variability models, that would model systematic intra-die variations. The models convert the variation in process into variation in electrical parameters of devices and hence variation in circuit performance (timing and leakage) without the need for circuit simulation. And as the analysis and mitigation techniques are studied in different levels of the design ow, we proposed a flow for combating the systematic process variation in nano-meter CMOS technology. By calculating the effects of variability on the electrical performance of circuits we can gauge the importance of the accurate analysis and model-driven corrections. We presented an automated framework that allows the integration of circuit analysis with process variability modeling to optimize the computer intense process simulation steps and optimize the usage of variation mitigation techniques. And we used the results obtained from using this framework to develop a relation between layout regularity and resilience of the devices to process variation. We used these findings to develop a novel technique for fast detection of critical failures (hotspots) resulting from process variation. We showed that our approach is superior to other published techniques in both accuracy and predictability. Finally, we presented an automated method for fixing the lithography hotspots. Our method showed success rate of 99% in fixing hotspots

    A Systems Engineering Reference Model for Fuel Cell Power Systems Development

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    This research was done because today the Fuel Cell (FC) Industry is still in its infancy in spite over one-hundred years of development has transpired. Although hundreds of fuel cell developers, globally have been spawned, in the last ten to twenty years, only a very few are left struggling with their New Product Development (NPD). The entrepreneurs of this type of disruptive technology, as a whole, do not have a systems engineering \u27roadmap , or template, which could guide FC technology based power system development efforts to address a more environmentally friendly power generation. Hence their probability of achieving successful commercialization is generally, quite low. Three major problems plague the fuel cell industry preventing successful commercialization today. Because of the immaturity of FC technology and, the shortage of workers intimately knowledgeable in FC technology, and the lack of FC systems engineering, process developmental knowledge, the necessity for a commercialization process model becomes evident. This thesis presents a six-phase systems engineering developmental reference model for new product development of a Solid Oxide Fuel Cell (SOFC) Power System. For this work, a stationary SOFC Power System, the subject of this study, was defined and decomposed into a subsystems hierarchy using a Part Centric Top-Down, integrated approach to give those who are familiar with SOFC Technology a chance to learn systems engineering practices. In turn, the examination of the SOFC mock-up could gave those unfamiliar with SOFC Technology a chance to learn the basic, technical fundamentals of fuel cell development and operations. A detailed description of the first two early phases of the systems engineering approach to design and development provides the baseline system engineering process details to create a template reference model for the remaining four phases. The NPD reference template model\u27s systems engineering process, philosophy and design tools are presented in great detail. Lastly, the thesi

    A Systems Engineering Reference Model for Fuel Cell Power Systems Development

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    This research was done because today the Fuel Cell (FC) Industry is still in its infancy in spite over one-hundred years of development has transpired. Although hundreds of fuel cell developers, globally have been spawned, in the last ten to twenty years, only a very few are left struggling with their New Product Development (NPD). The entrepreneurs of this type of disruptive technology, as a whole, do not have a systems engineering \u27roadmap , or template, which could guide FC technology based power system development efforts to address a more environmentally friendly power generation. Hence their probability of achieving successful commercialization is generally, quite low. Three major problems plague the fuel cell industry preventing successful commercialization today. Because of the immaturity of FC technology and, the shortage of workers intimately knowledgeable in FC technology, and the lack of FC systems engineering, process developmental knowledge, the necessity for a commercialization process model becomes evident. This thesis presents a six-phase systems engineering developmental reference model for new product development of a Solid Oxide Fuel Cell (SOFC) Power System. For this work, a stationary SOFC Power System, the subject of this study, was defined and decomposed into a subsystems hierarchy using a Part Centric Top-Down, integrated approach to give those who are familiar with SOFC Technology a chance to learn systems engineering practices. In turn, the examination of the SOFC mock-up could gave those unfamiliar with SOFC Technology a chance to learn the basic, technical fundamentals of fuel cell development and operations. A detailed description of the first two early phases of the systems engineering approach to design and development provides the baseline system engineering process details to create a template reference model for the remaining four phases. The NPD reference template model\u27s systems engineering process, philosophy and design tools are presented in great detail. Lastly, the thesi

    Yield modeling for deep sub-micron IC design

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    Clock Generator Circuits for Low-Power Heterogeneous Multiprocessor Systems-on-Chip

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    In this work concepts and circuits for local clock generation in low-power heterogeneous multiprocessor systems-on-chip (MPSoCs) are researched and developed. The targeted systems feature a globally asynchronous locally synchronous (GALS) clocking architecture and advanced power management functionality, as for example fine-grained ultra-fast dynamic voltage and frequency scaling (DVFS). To enable this functionality compact clock generators with low chip area, low power consumption, wide output frequency range and the capability for ultra-fast frequency changes are required. They are to be instantiated individually per core. For this purpose compact all digital phase-locked loop (ADPLL) frequency synthesizers are developed. The bang-bang ADPLL architecture is analyzed using a numerical system model and optimized for low jitter accumulation. A 65nm CMOS ADPLL is implemented, featuring a novel active current bias circuit which compensates the supply voltage and temperature sensitivity of the digitally controlled oscillator (DCO) for reduced digital tuning effort. Additionally, a 28nm ADPLL with a new ultra-fast lock-in scheme based on single-shot phase synchronization is proposed. The core clock is generated by an open-loop method using phase-switching between multi-phase DCO clocks at a fixed frequency. This allows instantaneous core frequency changes for ultra-fast DVFS without re-locking the closed loop ADPLL. The sensitivity of the open-loop clock generator with respect to phase mismatch is analyzed analytically and a compensation technique by cross-coupled inverter buffers is proposed. The clock generators show small area (0.0097mm2 (65nm), 0.00234mm2 (28nm)), low power consumption (2.7mW (65nm), 0.64mW (28nm)) and they provide core clock frequencies from 83MHz to 666MHz which can be changed instantaneously. The jitter performance is compliant to DDR2/DDR3 memory interface specifications. Additionally, high-speed clocks for novel serial on-chip data transceivers are generated. The ADPLL circuits have been verified successfully by 3 testchip implementations. They enable efficient realization of future low-power MPSoCs with advanced power management functionality in deep-submicron CMOS technologies.In dieser Arbeit werden Konzepte und Schaltungen zur lokalen Takterzeugung in heterogenen Multiprozessorsystemen (MPSoCs) mit geringer Verlustleistung erforscht und entwickelt. Diese Systeme besitzen eine global-asynchrone lokal-synchrone Architektur sowie Funktionalität zum Power Management, wie z.B. das feingranulare, schnelle Skalieren von Spannung und Taktfrequenz (DVFS). Um diese Funktionalität zu realisieren werden kompakte Taktgeneratoren benötigt, welche eine kleine Chipfläche einnehmen, wenig Verlustleitung aufnehmen, einen weiten Bereich an Ausgangsfrequenzen erzeugen und diese sehr schnell ändern können. Sie sollen individuell pro Prozessorkern integriert werden. Dazu werden kompakte volldigitale Phasenregelkreise (ADPLLs) entwickelt, wobei eine bang-bang ADPLL Architektur numerisch modelliert und für kleine Jitterakkumulation optimiert wird. Es wird eine 65nm CMOS ADPLL implementiert, welche eine neuartige Kompensationsschlatung für den digital gesteuerten Oszillator (DCO) zur Verringerung der Sensitivität bezüglich Versorgungsspannung und Temperatur beinhaltet. Zusätzlich wird eine 28nm CMOS ADPLL mit einer neuen Technik zum schnellen Einschwingen unter Nutzung eines Phasensynchronisierers realisiert. Der Prozessortakt wird durch ein neuartiges Phasenmultiplex- und Frequenzteilerverfahren erzeugt, welches es ermöglicht die Taktfrequenz sofort zu ändern um schnelles DVFS zu realisieren. Die Sensitivität dieses Frequenzgenerators bezüglich Phasen-Mismatch wird theoretisch analysiert und durch Verwendung von kreuzgekoppelten Taktverstärkern kompensiert. Die hier entwickelten Taktgeneratoren haben eine kleine Chipfläche (0.0097mm2 (65nm), 0.00234mm2 (28nm)) und Leistungsaufnahme (2.7mW (65nm), 0.64mW (28nm)). Sie stellen Frequenzen von 83MHz bis 666MHz bereit, welche sofort geändert werden können. Die Schaltungen erfüllen die Jitterspezifikationen von DDR2/DDR3 Speicherinterfaces. Zusätzliche können schnelle Takte für neuartige serielle on-Chip Verbindungen erzeugt werden. Die ADPLL Schaltungen wurden erfolgreich in 3 Testchips erprobt. Sie ermöglichen die effiziente Realisierung von zukünftigen MPSoCs mit Power Management in modernsten CMOS Technologien

    NREL Photovoltaic Program FY 1995 annual report

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    Cooperative air traffic optimisation for minimum overall fuel usage

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    The objective of this research was to demonstrate that a continental-scale air traffic model, featuring cooperative user preferred trajectories (UPT), can be optimized to minimize total fuel usage. The model was based on the premise that the flight plans, i.e. routes with departure and arrival times, for all aircraft within a continental-scale region were known and their altitude and speed profiles were determined for minimum overall fuel burn, subject to conflict resolution; the resulting set of trajectories would require actions for all involved aircraft and thus be cooperative in nature. The model was also based on the premise that these flight plans would also contain information on the aircraft’s, and its corresponding airline’s, trajectory preferences in the form of UPT; preferences that did not prevent minimization of total fuel usage, or cooperative action towards it, were incorporated into the model. The research integrated air traffic and aircraft performance models around an Interior Point Optimisation technique. Each aircraft’s speed and altitude along the aircraft’s route, was treated as a free variable within aircraft performance limits; the optimisation methodology determined the speed and altitude schedule for each aircraft to ensure total fuel usage was minimum. Constraints on minimum separation, aircraft performance limits and arrival time, were also included; unexpected heading changes and deviation due to adverse weather conditions were included in the optimisation. Further, the integration utilized a means of data transfer which was also found to efficiently define separation required by air traffic; this led to the development of a more efficient form of air traffic optimization. In order to take advantage of this new form, several novel concepts were tested and used, such as fuel usage optimization via Interior Point based algorithms, hyper ellipse based definitions of air traffic separation, and flexible trajectory control node distribution to suit different purposes. Afterwards, the optimization was improved further by including three more functionalities; Base of Aircraft Data (BADA) for aircraft performance modelling, Dynamic Re-optimization to handle unpredicted air traffic changes, and Control Node Customization of trajectory profiles to cater for UPT. The final result of this research was an air traffic optimizer with several notable attributes. First is that it optimizes individual aircraft trajectories to minimize fuel usage; no fuel usage inefficiencies due to aircraft clustering. Second is that it optimizes air traffic covering a continental sized area in a time frame that makes it feasible for actual use. Lastly is that it facilitates incorporation of all forms of Air Navigation Service Provider (ANSP), Airline, and Aircraft information into the optimization process; i.e. the process is holistic and accommodate a variety of air traffic stakeholder interests. ANSP data is incorporated as a model of ground and airspace specific properties and restrictions, airline and aircrew data are incorporated as properties of customizable UPT, and individual aircraft information are incorporated as the mechanics and constraints of air traffic and its fuel usage
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