Low Power and Improved Speed Montgomery Multiplier using Universal Building Blocks

This paper describes the arithmetic blocks based on Montgomery Multiplier (MM), which reduces complexity, gives lower power dissipation and higher operating frequency. The main objective in designing these arithmetic blocks is to use modified full adder structure and carry save adder structure that can be implemented in algorithm based MM circuit. The conventional full adder design acts as a benchmark for comparison, the second is the modified Boolean equation for full adder and third design is the design of full adder consisting of two XOR gate and a 2-to-1 Multiplexer. Besides Universal gates such as NOR gate and NAND gate, full adder circuits are used to further improve the speed of the circuit. The MM circuit is evaluated based on different parameters such as operating frequency, power dissipation and area of occupancy in FPGA board. The schematic designs of the arithmetic components along with the MM architecture are constructed using Quartus II tool, while the simulation is done using Model sim for verification of circuit functionality which has shown improvement on the full adder design with two XOR gate and one 2-to-1 Multiplexer implementation in terms of power dissipation, operating frequency and area

Cryogenic Control Beyond 100 Qubits

Quantum computation has been a major focus of research in the past two decades, with recent experiments demonstrating basic algorithms on small numbers of qubits. A large-scale universal quantum computer would have a profound impact on science and technology, providing a solution to several problems intractable for classical computers. To realise such a machine, today's small experiments must be scaled up, and a system must be built which provides control and measurement of many hundreds of qubits. A device of this scale is challenging: qubits are highly sensitive to their environment, and sophisticated isolation techniques are required to preserve the qubits' fragile states. Solid-state qubits require deep-cryogenic cooling to suppress thermal excitations. Yet current state-of-the-art experiments use room-temperature electronics which are electrically connected to the qubits. This thesis investigates various scalable technologies and techniques which can be used to control quantum systems. With the requirements for semiconductor spin-qubits in mind, several custom electronic systems, to provide quantum control from deep cryogenic temperatures, are designed and measured. A system architecture is proposed for quantum control, providing a scalable approach to executing quantum algorithms on a large number of qubits. Control of a gallium arsenide qubit is demonstrated using a cryogenically operated FPGA driving custom gallium arsenide switches. The cryogenic performance of a commercial FPGA is measured, as the main logic processor in a cryogenic quantum control system, and digital-to-analog converters are analysed during cryogenic operation. Recent work towards a 100-qubit cryogenic control system is shown, including the design of interconnect solutions and multiplexing circuitry. With qubit fidelity over the fault-tolerant threshold for certain error correcting codes, accompanying control platforms will play a key role in the development of a scalable quantum machine

Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices

This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results

Investigating Opportunities and Challenges in Modeling and Designing Scale-Out DNN Accelerators

The rapid growth of deep learning used in practical applications such as speech recognition, computer vision, natural language processing, robotics, any many other fields has opened the gate to new technology possibilities. Unfortunately, traditional hardware systems are being stretched to the maximum to accommodate the intense workloads presented by state-of-the-art deep learning processes in a time when transistor technology is not scaling. To serve the demand for better computational power and more specialized computations, specialized hardware needs to be developed that provides better latency and bandwidth specifications for various demanding applications. The trend in the semi-conductor industry is to move towards heterogenous System-On Chip (SoC) thereby choosing application specific performance vs. generality seen in most CPU architectures today. In most situations, hardware engineers are left to construct systems that serve the needs of various applications, often needing to predict the use-cases of the system. As with any field, the ability to predict and act on the future innovation trends of the industry is the difference between success and failure. A novel simulator for the design of convolutional neural network accelerators is presented and described in detail named SCALE-Sim (Systolic CNN Accelerator Simulator). The simulator is available as an open-sourced repository and has 2 primary use-cases in which computer architects can extract significant results. The first use-case is for system designers who would like to integrate an existing DNN accelerator architecture into a larger SoC and would be interested in system-level characterization results. The second use-case is for an accelerator architect who would like to use the tool to explore the accelerator design space by sweeping through design parameters.M.S

Crexens™: an expandable general-purpose electrochemical analyzer

2019 Fall.Includes bibliographical references.Electrochemical analysis has gained a great deal of attention of late due to its low-cost, easy-to-perform, and easy-to-miniaturize, especially in personal health care where accuracy and mobility are key factors to bring diagnostics to patients. According to data from Centers for Medicare & Medicaid Services (CMS) in the US, the share of health expenditure in the US has been kept growing in the past 3 decades and reached 17.9% of its overall Gross Domestic Product till 2016, which is equivalent to $10,348 for every person in the US per year. On the other hand, health care resources are often limited not only in rural area but also appeared in well-developed countries. The urgent need and the lack of health resource brings to front the research interest of Point-of-Care (PoC) diagnosis devices. Electrochemical methods have been largely adopted by chemist and biologist for their research purposes. However, several issues exist within current commercial benchtop instruments for electrochemical measurement. First of all, the current commercial instruments are usually bulky and do not have handheld feature for point-of-care applications and the cost are easily near$5,000 each or above. Secondly, most of the instruments do not have good integration level that can perform different types of electrochemical measurements for different applications. The last but not the least, the existing generic benchtops instruments for electrochemical measurements have complex operational procedures that require users to have a sufficient biochemistry and electrochemistry background to operate them correctly. The proposed Crexens™ analyzer platform is aimed to present an affordable electrochemical analyzerwhile achieving comparable performance to the existing commercial instruments, thus, making general electrochemical measurement applications accessible to general public. In this dissertation, the overall Crexens™ electrochemical analyzer architecture and its evolution are presented. The foundation of the Crexens™ architecture was derived from two separate but related research in electrochemical sensing. One of them is a microelectrode sensor array using CMOS for neurotransmitter sensing; the other one is a DNA affinity-based capacitive sensor for infectious disease, such as ZIKA. The CMOS microelectrode sensor array achieved a 320uM sensitivity for norepinephrine, whereas the capacitive sensor achieved a dynamic range of detection from 1 /uL to 105 /uL target molecules (20 to 2 million targets), which makes it be within the detection range in a typical clinical application environment. This dissertation also covers the design details of the CMOS microelectrode array sensor and the capacitive sensor design as a prelude to the development of the Crexens™ analyzer architecture. Finally, an expandable integrated electrochemical analyzer architecture (Crexens™) has been designed for mobile point-of-care (POC) applications. Electrochemical methods have been explored in detecting various bio-molecules such as glucose, lactate, protein, DNA, neurotransmitter, steroid hormone, which resulted in good sensitivity and selectivity. The proposed system is capable of running electrochemical experiments including cyclic voltammetry (CV), electrochemical impedance spectroscopy (EIS), electrochemical capacitive spectroscopy (ECS), amperometry, potentiometry, and other derived electrochemical based tests. This system consist of a front-end interface to sensor electrodes, a back-end user interface on smart phone and PC, a base unit as master module, a low-noise add-on module, a high-speed add-on module, and a multi-channel add-on module. The architecture allows LEGO™-like capability to stack add-on modules on to the base-unit for performance enhancements in noise, speed or parallelism. The analyzer is capable of performing up to 1900 V/s CV with 10 mV step, up to 12 kHz EIS scan range and a limit of detection at 637 pA for amperometric applications with the base module. With high performance module, the EIS scan range can be extended upto 5 MHz. The limit of detection can be further improved to be at 333 fA using the low-noise module. The form factor of the electrochemical analyzer is designed for its mobile/point-of-care applications, integrating its entire functionality on to a 70 cm² area of surface space. A glutamine enzymatic sensor was used to valid the capability of the proposed electrochemical analyzer and turned out to give good linearity and reached a limit of detection at 50 uM

RSFQ 4-bit bit-slice integer multiplier

A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-μm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n x 4n-bit multiplier consists of 2n + 17 stages. For verifying the algorithm and the logic design, a physical layout of the 8 x 8-bit multiplier has been designed with target operating frequency of 50 GHz and simulated. It consists of 21 stages and 11, 488 Josephson junctions. The simulation results show correct operation up to 62.5 GHz

Understanding Quantum Technologies 2022

Understanding Quantum Technologies 2022 is a creative-commons ebook that provides a unique 360 degrees overview of quantum technologies from science and technology to geopolitical and societal issues. It covers quantum physics history, quantum physics 101, gate-based quantum computing, quantum computing engineering (including quantum error corrections and quantum computing energetics), quantum computing hardware (all qubit types, including quantum annealing and quantum simulation paradigms, history, science, research, implementation and vendors), quantum enabling technologies (cryogenics, control electronics, photonics, components fabs, raw materials), quantum computing algorithms, software development tools and use cases, unconventional computing (potential alternatives to quantum and classical computing), quantum telecommunications and cryptography, quantum sensing, quantum technologies around the world, quantum technologies societal impact and even quantum fake sciences. The main audience are computer science engineers, developers and IT specialists as well as quantum scientists and students who want to acquire a global view of how quantum technologies work, and particularly quantum computing. This version is an extensive update to the 2021 edition published in October 2021.Comment: 1132 pages, 920 figures, Letter forma

References, Appendices & All Parts Merged

Includes: Appendix MA: Selected Mathematical Formulas; Appendix CA: Selected Physical Constants; References; EGP merged file (all parts, appendices, and references)https://commons.library.stonybrook.edu/egp/1007/thumbnail.jp