Bit-Error-Rate-Minimizing Channel Shortening Using Post-FEQ Diversity Combining and a Genetic Algorithm

In advanced wireline or wireless communication systems, i.e., DSL, IEEE 802.11a/g, HIPERLAN/2, etc., a cyclic prefix which is proportional to the channel impulse response is needed to append a multicarrier modulation (MCM) frame for operating the MCM accurately. This prefix is used to combat inter symbol interference (ISI). In some cases, the channel impulse response can be longer than the cyclic prefix (CP). One of the most useful techniques to mitigate this problem is reuse of a Channel Shortening Equalizer (CSE) as a linear preprocessor before the MCM receiver in order to shorten the effective channel length. Channel shortening filter design is a widely examined topic in the literature. Most channel shortening equalizer proposals depend on perfect channel state information (CSI). However, this information may not be available in all situations. In cases where channel state information is not needed, blind adaptive equalization techniques are appropriate. In wireline communication systems (such as DMT), the CSE design is based on maximizing the bit rate, but in wireless systems (OFDM), there is a fixed bit loading algorithm, and the performance metric is Bit Error Rate (BER) minimization. In this work, a CSE is developed for multicarrier and single-carrier cyclic prefixed (SCCP) systems which attempts to minimize the BER. To minimize the BER, a Genetic Algorithm (GA), which is an optimization method based on the principles of natural selection and genetics, is used. If the CSI is shorter than the CP, the equalization can be done by a frequency domain equalizer (FEQ), which is a bank of complex scalars. However, in the literature the adaptive FEQ design has not been well examined. The second phase of this thesis focuses on different types of algorithms for adapting the FEQ and modifying the FEQ architecture to obtain a lower BER. Simulation results show that this modified architecture yields a 20 dB improvement in BER

Low complexity channel shortening and equalization for multi-carrier systems

A new time domain blind adaptive channel shortening algorithm for Discrete Multi Tone (DMT)-based multicarrier systems is first proposed. It is computationally less expensive, and more robust to non- Gaussian impulsive noise environments than a recently reported Sum squared Autocorrelation Minimization (SAM) algorithm. A "left" initialization scheme is also suggested for Carrier Serving Area (CSA) loop Asymmetric Digital Subscriber Line (ADSL) channels. Simulation studies show that by a proper selection of the learning parameter i.e., the step size, the bit rates achieved by the SAM algorithm when operating in an environment contaminated by Additive White Gaussian Noise (AWGN) can be further improved. Next a novel time domain low complexity blind adaptive channel short ening algorithm called Single Lag Autocorrelation Minimization (SLAM) is introduced. The algorithm is totally blind in the sense that it does not require a prior knowledge about the length of the channel impulse response. The proposed novel stopping criterion freezes the adaptation of the SLAM algorithm when the maximum amount of Inter Symbol Interference (ISI) is cancelled. As such, the stopping criterion can also be used with SAM. An attractive alternate frequency domain equalization approach for multicarrier systems is Per Tone Equalization (PTEQ). This scheme en- ables true signal-tonoise ratio optimization to be implemented for each tone and it always achieves higher bit rates than Time domain Equalizer (TEQ) based channel shortening schemes but at the price of increased computational complexity and higher memory requirements. A low complexity (PTEQ) scheme is, therefore, finally proposed. The com plexity of the PTEQ can be traded off with the complexity of the timing synchronization within the system. In particular, it is shown that the use of more than one difference terms and hence a long equalizer in the PTEQ scheme is generally redundant. The PTEQ scheme assumes knowledge of the channel impulse response. In this case synchronization is trivial and it is possible to use only a length two PTEQ equalizer and attain essentially identical bit rate performance to a PTEQ equalizer with length matched to the cyclic prefix. This observation allows for a substantial reduction in computational complexity of the PTEQ scheme in both initialization and data transmission modes. For a reasonable range of values of synchronization error, <5, around the optimal value of 5 = 0, the performance of this length two equalizer is shown to remain relatively constant. For positive synchronization errors, however, the required PTEQ equalizer length is proportional to the synchronization error. A low complexity blind synchronization method is ultimately suggested which is based on the construction of the difference terms of the PTEQ scheme

FPGA-based DOCSIS upstream demodulation

In recent years, the state-of-the-art in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of advantages over ASIC-based designs, including lower up-front engineering design costs, shorter time-to-market, and the ability to reconfigure devices in the field. However, ASICs have a major advantage in terms of computational resources. As a result, expensive high performance ASIC algorithms must be redesigned to fit the limited resources available in an FPGA. Concurrently, coaxial cable television and internet networks have been undergoing significant upgrades that have largely been driven by a sharp increase in the use of interactive applications. This has intensified demand for the so-called upstream channels, which allow customers to transmit data into the network. The format and protocol of the upstream channels are defined by a set of standards, known as DOCSIS 3.0, which govern the flow of data through the network. Critical to DOCSIS 3.0 compliance is the upstream demodulator, which is responsible for the physical layer reception from all customers. Although upstream demodulators have typically been implemented as ASICs, the design of an FPGA-based upstream demodulator is an intriguing possibility, as FPGA-based demodulators could potentially be upgraded in the field to support future DOCSIS standards. Furthermore, the lower non-recurring engineering costs associated with FPGA-based designs could provide an opportunity for smaller companies to compete in this market. The upstream demodulator must contain complicated synchronization circuitry to detect, measure, and correct for channel distortions. Unfortunately, many of the synchronization algorithms described in the open literature are not suitable for either upstream cable channels or FPGA implementation. In this thesis, computationally inexpensive and robust synchronization algorithms are explored. In particular, algorithms for frequency recovery and equalization are developed. The many data-aided feedforward frequency offset estimators analyzed in the literature have not considered intersymbol interference (ISI) caused by micro-reflections in the channel. It is shown in this thesis that many prominent frequency offset estimation algorithms become biased in the presence of ISI. A novel high-performance frequency offset estimator which is suitable for implementation in an FPGA is derived from first principles. Additionally, a rule is developed for predicting whether a frequency offset estimator will become biased in the presence of ISI. This rule is used to establish a channel excitation sequence which ensures the proposed frequency offset estimator is unbiased. Adaptive equalizers that compensate for the ISI take a relatively long time to converge, necessitating a lengthy training sequence. The convergence time is reduced using a two step technique to seed the equalizer. First, the ISI equivalent model of the channel is estimated in response to a specific short excitation sequence. Then, the estimated channel response is inverted with a novel algorithm to initialize the equalizer. It is shown that the proposed technique, while inexpensive to implement in an FPGA, can decrease the length of the required equalizer training sequence by up to 70 symbols. It is shown that a preamble segment consisting of repeated 11-symbol Barker sequences which is well-suited to timing recovery can also be used effectively for frequency recovery and channel estimation. By performing these three functions sequentially using a single set of preamble symbols, the overall length of the preamble may be further reduced

Single-Frequency Network Terrestrial Broadcasting with 5GNR Numerology

L'abstract è presente nell'allegato / the abstract is in the attachmen

Split SR-RLS for the Joint Initialization of the Per-Tone Equalizers and Per-Tone Echo Cancelers in DMT-Based Receivers

In asymmetric digital subscriber lines (ADSL), the available bandwidth is divided in subcarriers or tones which are assigned to the upstream and/or downstream transmission direction. To allow efficient bidirectional communication over one twisted pair, echo cancellation is required to separate upstream and downstream channels. In addition, intersymbol interference and intercarrier interference have to be reduced by means of equalization. In this paper, a computationally efficient algorithm for adaptively initializing the per-tone equalizers (PTEQ) and per-tone echo cancelers (PTEC) is presented. For a given number of equalizer and echo canceler taps per-tone, it was shown that the joint PTEQ/PTEC receiver structure is able to maximize the signal-to-noise ratio (SNR) on each subcarrier and hence also the achievable bit rate. The proposed initialization scheme is based on a modification of the square root recursive least squares (SR-RLS) algorithm to reduce computational complexity and memory requirement compared to full SR-RLS, while keeping the convergence rate acceptably fast. Our performance analysis will show that the proposed method converges in the mean and an upper bound for the step size is given. Moreover, we will indicate how the presented initialization method can be reused in several other ADSL applications