Optical interconnect solution with plasmonic modulator and Ge photodetector array

We report on an optical chip-to-chip interconnect solution, thereby demonstrating plasmonics as a solution for ultra-dense, high-speed short-reach communications. The interconnect comprises a densely integrated plasmonic Mach-Zehnder modulator array that is packaged with standard driving electronics. On the receiver side, a germanium photodetector array is integrated with trans-impedance amplifiers. A multicore fiber provides a compact optical interface to the array. We demonstrate 4 × 20 Gb/s on-off keying signaling with direct detection.ISSN:1041-1135ISSN:1941-017

Optical interconnect with densely integrated plasmonic modulator and germanium photodetector arrays

We demonstrate the first chip-to-chip interconnect utilizing a densely integrated plasmonic Mach-Zehnder modulator array operating at 3 x 10 Gbit/s. A multicore fiber provides a compact optical interface, while the receiver consists of germanium photodetectors

Wavelength-multiplexed duplex transceiver based on III-V/Si hybrid integration for off-chip and on-chip optical interconnects

A six-channel wavelength-division-multiplexed optical transceiver with a compact footprint of 1.5 x 0.65 mm(2) for off-chip and on-chip interconnects is demonstrated on a single silicon-on-insulator chip. An arrayed waveguide grating is used as the (de)multiplexer, and III-V electroabsorption sections fabricated by hybrid integration technology are used as both modulators and detectors, which also enable duplex links. The 30-Gb/s capacity for each of the six wavelength channels for the off-chip transceiver is demonstrated. For the on-chip interconnect, an electrical-to-electrical 3-dB bandwidth of 13 GHz and a data rate of 30 Gb/s per wavelength are achieved

Inherently workload-balanced clustered microarchitecture

The performance of clustered microarchitectures relies on steering schemes that try to find the best trade-off between workload balance and inter-cluster communication penalties. In previously proposed clustered processors, reducing communication penalties and balancing the workload are opposite targets, since improving one usually implies a detriment in the other. In this paper we propose a new clustered microarchitecture that can minimize communication penalties without compromising workload balance. The key idea is to arrange the clusters in a ring topology in such a way that results of one cluster can be forwarded to the neighbor cluster with a very short latency. In this way, minimizing communication penalties is favored when the producer of a value and its consumer are placed in adjacent clusters, which also favors workload balance. The proposed microarchitecture is shown to outperform a state-of-the-art clustered processor. For instance, for an 8-cluster configuration and just one fully pipelined unidirectional bus, 15% speedup is achieved on average for FP programs.Peer ReviewedPostprint (published version

Silicon optical modulators

Optical technology is poised to revolutionise short reach interconnects. The leading candidate technology is silicon photonics, and the workhorse of such interconnect is the optical modulator. Modulators have been improved dramatically in recent years. Most notably the bandwidth has increased from the MHz to the multi GHz regime in little more than half a decade. However, the demands of optical interconnect are significant, and many questions remain unanswered as to whether silicon can meet the required performance metrics. Minimising metrics such as the energy per bit, and device footprint, whilst maximising bandwidth and modulation depth are non trivial demands. All of this must be achieved with acceptable thermal tolerance and optical spectral width, using CMOS compatible fabrication processes. Here we discuss the techniques that have, and will, be used to implement silicon optical modulators, as well as the outlook for these devices, and the candidate solutions of the future