Integrated Silicon Microwave and Millimeterwave Passive Components and Functions

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Manufacture and Characterization of High Q-Factor Inductors Based on CMOS-MEMS Techniques

A high Q-factor (quality-factor) spiral inductor fabricated by the CMOS (complementary metal oxide semiconductor) process and a post-process was investigated. The spiral inductor is manufactured on a silicon substrate. A post-process is used to remove the underlying silicon substrate in order to reduce the substrate loss and to enhance the Q-factor of the inductor. The post-process adopts RIE (reactive ion etching) to etch the sacrificial oxide layer, and then TMAH (tetramethylammonium hydroxide) is employed to remove the silicon substrate for obtaining the suspended spiral inductor. The advantage of this post-processing method is its compatibility with the CMOS process. The performance of the spiral inductor is measured by an Agilent 8510C network analyzer and a Cascade probe station. Experimental results show that the Q-factor and inductance of the spiral inductor are 15 at 15 GHz and 1.8 nH at 1 GHz, respectively

Reconfigurable Impedance Matching Networks Based on RF-MEMS and CMOS-MEMS Technologies

Reconfigurable impedance matching networks are an integral part of multiband radio-frequency (RF) transceivers. They are used to compensate for the input/output impedance variations between the different blocks caused by switching the frequency band of operation or by adjusting the output power level. Various tuning techniques have been developed to construct tunable impedance matching networks employing solid-state p-i-n diodes and varactors. At millimeter-wave frequencies, the increased loss due to the low quality factor of the solid-state devices becomes an important issue. Another drawback of the solid-state tuning elements is the increased nonlinearity and noise at higher RF power levels. The objective of the research described in this thesis is to investigate the feasibility of using RF microelectromechanical systems (RF-MEMS) technology to develop reconfigurable impedance matching networks. Different types of tunable impedance matching networks with improved impedance tuning range, power handling capability, and lower insertion loss have been developed. Another objective is to investigate the realization of a fully integrated one-chip solution by integrating MEMS devices in standard processes used for RF integrated circuits (RFICs). A new CMOS-MEMS post-processing technique has been developed that allows the integration of tunable RF MEMS devices with vertical actuation within a CMOS chip. Various types of CMOS-MEMS components used as tuning elements in reconfigurable RF transceivers have been developed. These include tunable parallel-plate capacitors that outperform the available CMOS solid-state varactors in terms of quality factor and linearity. A tunable microwave band-pass filter has been demonstrated by employing the proposed RF MEMS tunable capacitors. For the first time, CMOS-MEMS capacitive type switches for microwave and millimeter-wave applications have been developed using TSMC 0.35-µm CMOS process employing the proposed CMOS-MEMS integration technique. The switch demonstrates an excellent RF performance from 10-20 GHz. Novel MEMS-based reconfigurable impedance matching networks integrated in standard CMOS technologies are also presented. An 8-bit reconfigurable impedance matching network based on the distributed MEMS transmission line (DMTL) concept operating at 13-24 GHz is presented. The network is implemented using standard 0.35-µm CMOS technology and employs a novel suspended slow-wave structure on a silicon substrate. To our knowledge, this is the first implementation of a DMTL tunable MEMS impedance matching network using a standard CMOS technology. A reconfigurable amplifier chip for WLAN applications operating at 5.2 GHz is also designed and implemented. The amplifier achieves maximum power gain under variable load and source impedance conditions by using the integrated RF-MEMS impedance matching networks. This is the first single-chip implementation of a reconfigurable amplifier using high-Q MEMS impedance matching networks. The monolithic CMOS implementation of the proposed RF MEMS impedance matching networks enables the development of future low-cost single-chip RF multiband transceivers with improved performance and functionality

Copper / low-k technological platform for the fabrication of high quality factor above-IC passive devices

Modern communication devices demand challenging specifications in terms of miniaturization, performance, power consumption and cost. Every new generation of radio frequency integrated circuits (RF-ICs) offer better functionality at reduced size, power consumption and cost per device and per integrated function. Passive devices (resistors, inductors, capacitors, antennas and transmission lines) represent an important part of the cost and size of RF circuits. These components have not evolved at the same level of the transistor devices, especially because their performance is strongly degenerated when they scale down in size. The low resistivity silicon used to build the transistors also imposes prohibitive levels of RF losses to these passive devices. Radio frequency microelectromechanical systems (RF MEMS) are enabling technologies capable to bring significant improvement in the electrical performances and expressive size and cost reduction of these functions, with unparallel introduction of new functionalities, unimaginable to attain when using bulky, externally connected discrete components. High quality factor (Q) inductors are amongst ones of the most needed components in RF circuits and at the same time ones that are most affected by thin metallization and substrate related losses, demanding considerable research effort. This thesis presents a contribution toward the development of thick metal fabrication technologies, covering also the design, modeling and characterization of high quality factor and high self-resonant frequency (SRF) RF MEMS passive devices, with a special emphasis on spiral inductors. A new approach using damascene-like interconnect fabrication steps associated to low κ dielectrics (polyimide), highly-conductive thick copper electroplating, chemical mechanical polishing (CMP) and tailored substrate properties delivered quality factors in excess of 40 and self resonant frequencies in excess of 10 GHz, performances in the current state-of-the-art for integrated spiral inductors built on top of silicon wafers. Furthermore, the developed process steps are compatible with back-end processing used to fabricate modern IC interconnects and have a low thermal budget (< 250 °C), what makes it a good choice to build above-IC passives without degenerating the performance of passivated RF-CMOS circuits. Deep reactive ion etching (DRIE) of quartz substrates was also studied for the fabrication of spiral inductors, offering excellent RF performances (Q exceeding 40 and SRF exceeding 7 GHz). A new doubly-functional quartz packaging concept for RF MEMS devices was developed. This technique process both sides of the packaging wafer: the top is used to embed high quality factor copper inductors while the bottom is thermo-mechanically bonded to another RF MEMS wafer, offering a semi-hermetic SU-8 epoxy-based seal. The bonding process was optimized for high yield, to be compatible with SF6-plasma-released MEMS and to present low level of RF losses. Band pass filters for the GSM (1.8 GHz) and WLAN (5.2 GHz) standards were fabricated and characterized by RF measurements and full wave electromagnetic simulations. Although further development is need in order to predict the frequency response accurately, insertion losses as low as 1.2 dB were demonstrated, levels that cannot be usually attained using on-chip passives. Systematic analysis, RF measurements, electromagnetic simulations and equivalent circuit extraction were used to model the behavior of the fabricated devices and establish a methodology to deliver optimum performances for a given technological profile and specified performance targets (quality factor, inductance and frequency bandwidth). A simple yet accurate physics-based analytical model for spiral inductors was developed and proved to be accurate in terms of loss estimation for thick metal layers. This model is capable to accurately describe the frequency-dependent behavior of the device below its first resonant frequency over a large device design space. The model was validated by both measurements and full wave electromagnetic simulations and is well suited to perform numeric optimization of designs. The proposed models were also systematized in a Matlab® toolbox

Above-IC RF MEMS devices for communication applications

Wireless communications are showing an explosive growth in emerging consumer and military applications of radiofrequency (RF), microwave, and millimeter-wave circuits and systems. Applications include wireless personal connectivity (Bluetooth), wireless local area networks (WLAN), mobile communication systems (GSM, GPRS, UMTS, CDMA), satellite communications and automotive electronics. Future cell phones and ground communication systems as well as communication satellites will require more and more sophisticated technologies. The increasing demand for size and weight reduction, cost savings, low power consumption, increased frequency and higher functionality and reconfigurability as part of multiband and multistandard operation is necessitating the use of highly integrated RF front-end circuits. Chip scaling has made a major contribution to this goal, but today a situation has been reached where the presence of numerous off-chip passive RF components imposes a critical bottleneck to further integration and miniaturization of wireless transceivers. Microelectromechanical systems (MEMS) technology is a rapidly emerging enabling technology that is intended to replace the discrete passives by their integrated counterparts. In this thesis, an original metal surface micromachining process, which is compatible with CMOS post-processing, for above-IC integration of RF MEMS tunable capacitors and suspended inductors is presented. A detailed study on SF6 inductively coupled plasma (ICP) releasing has been performed in order to ascertain the optimal process parameters. This study has emphasized the fact that temperature plays an important role in this process by limiting silicon dioxide etching. Moreover, the optimized recipe has been found to be independent of the sacrificial layer used (amorphous or polycrystalline silicon) and its thickness. Using this recipe, 15.6 µm/min Si underetch rate with high Si: SiO2 selectivity (> 20000: 1) has been obtained. Single-air-gap and double-air-gap parallel-plate MEMS tunable capacitors have been designed, fabricated and characterized in the pF range, from 1 MHz to 13.5 GHz. It has been shown that an optimized design of the suspended membrane and direct symmetrical current feed at both ports can significantly improve the quality factor and increase the self-resonant frequency, pushing it to 12 GHz and beyond. The maximum capacitance tuning range obtained for a single-air-gap capacitor is 29% for a bias voltage of 20 V. The maximum capacitance tuning range obtained for a double-air-gap capacitor is 207% for a bias voltage of 70 V. The post-processing of X-FAB BiCMOS wafers has been successfully demonstrated to fabricate monolithically integrated VCOs with above-IC MEMS LC tank. Comparing a suspended inductor and the X-FAB inductor with the same design, it has been shown that increasing the thickness of the spiral from 2.3 to 4 µm and having the spiral suspended 3 µm above the passivation layers lead to an improvement factor of 2 for the peak quality factor and a shift of the self-resonant frequency beyond 15 GHz. No significant variation on bipolar and MOS transistors characteristics due to the post-processing has been observed and we conclude that the variation due to post-processing is in the same range as the wafer-to-wafer variation. Based on our metal surface micromachining process, coplanar waveguide (CPW) MEMS shunt capacitive switches and variable true-time delay lines (V-TTDLs) have been designed, fabricated and characterized in the 1 - 20 GHz range. A novel MEMS device architecture: the SG-MOSFET, which combines a solid-state MOS transistor and a metal suspended gate has been proposed as DC current switch. The corresponding fabrication process using polysilicon as a sacrificial layer has been developed to release metal gate suspended over gate oxide by SF6 plasma. Very abrupt current switches have been demonstrated with subthreshold slope better than 10 mV/decade (better than the theoretical solid-state bulk or SOI MOSFET limit of 60 mV/decade) and ultra-low gate leakage (less than 0.001 pA/µm2) due to the air-gap

Superconducting routing platform for large-scale integration of quantum technologies

To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspective in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridization of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al0.995Cu0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies and low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented

Methods For Fabricating Three-dimensional All Organic Interconnect Structures

The present invention includes methods for making liquid crystalline polymer (LCP) interconnect structures using a high temperature and low temperature single sided liquid crystalline polymer LCP where both the high and low temperature LCP are drilled to form a z-axis connection. The single sided conductive layer is a bus layer to form z axis conductive stud within the high and low temperature LCP, followed by a metallic capping layer of the stud that serves as the bonding metal between the conductive interconnects to form the z-axis connection. High and low temperature LCP layers are etched or built up to form circuit patterns and subsequently bonded together to form final multilayer circuit pattern where the low temperature LCP melts to form both dielectric to dielectric bond to high temperature LCP circuit layer, and dielectric to conductive bond, whereas metal to metal bonding occurs with high temperature metal capping layer bonding to conductive metal layer.Georgia Tech Research Corporatio