A self-powered single-chip wireless sensor platform

Internet of things” require a large array of low-cost sensor nodes, wireless connectivity, low power operation and system intelligence. On the other hand, wireless biomedical implants demand additional specifications including small form factor, a choice of wireless operating frequencies within the window for minimum tissue loss and bio-compatibility This thesis describes a low power and low-cost internet of things system suitable for implant applications that is implemented in its entirety on a single standard CMOS chip with an area smaller than 0.5 mm2. The chip includes integrated sensors, ultra-low-power transceivers, and additional interface and digital control electronics while it does not require a battery or complex packaging schemes. It is powered through electromagnetic (EM) radiation using its on-chip miniature antenna that also assists with transmit and receive functions. The chip can operate at a short distance (a few centimeters) from an EM source that also serves as its wireless link. Design methodology, system simulation and optimization and early measurement results are presented

Architecture of Micro Energy Harvesting Using Hybrid Input of RF, Thermal and Vibration for Semi-Active RFID Tag

This research work presents a novel architecture of Hybrid Input Energy Harvester (HIEH) system for semi-active Radio Frequency Identification (RFID) tags. The proposed architecture consists of three input sources of energy which are radio frequency signal, thermal and vibration. The main purpose is to solve the semi-active RFID tags limited lifespan issues due to the need for batteries to power their circuitries. The focus will be on the rectifiers and DC-DC converter circuits with an ultra-low power design to ensure low power consumption in the system. The design architecture will be modelled and simulated using PSpice software, Verilog coding using Mentor Graphics and real-time verification using field-programmable gate array board before being implemented in a 0.13 µm CMOS technology. Our expectations of the results from this architecture are it can deliver 3.3 V of output voltage, 6.5 mW of output power and 90% of efficiency when all input sources are simultaneously harvested. The contribution of this work is it able to extend the lifetime of semi-active tag by supplying electrical energy continuously to the device. Thus, this will indirectly  reduce the energy limitation problem, eliminate the dependency on batteries and make it possible to achieve a batteryless device.This research work presents a novel architecture of Hybrid Input Energy Harvester (HIEH) system for semi-active Radio Frequency Identification (RFID) tags. The proposed architecture consists of three input sources of energy which are radio frequency signal, thermal and vibration. The main purpose is to solve the semi-active RFID tags limited lifespan issues due to the need for batteries to power their circuitries. The focus will be on the rectifiers and DC-DC converter circuits with an ultra-low power design to ensure low power consumption in the system. The design architecture will be modelled and simulated using PSpice software, Verilog coding using Mentor Graphics and real-time verification using field-programmable gate array board before being implemented in a 0.13 µm CMOS technology. Our expectations of the results from this architecture are it can deliver 3.3 V of output voltage, 6.5 mW of output power and 90% of efficiency when all input sources are simultaneously harvested. The contribution of this work is it able to extend the lifetime of semi-active tag by supplying electrical energy continuously to the device. Thus, this will indirectly  reduce the energy limitation problem, eliminate the dependency on batteries and make it possible to achieve a batteryless device

Chipless Radio Frequency Identification (RFID) Tag Utilizing Beamforming Technique

This work is a paper based dissertation which presents a new method to design low cost chipless radio-frequency identification (RFID) tags using MEMS technology. The proposed chipless tag can be batch-fabricated using a basic MEMS fabrication process. The chipless tag can operate over a wide range of frequencies including the conventional UHF band for RFID applications. The elimination of the chip can reduces the tag price to the extent that it becomes an alternative solution to barcode labels. A prototype of the tag is implemented using a basic fabrication process and measurements are performed to validate its functionality. For the RFID reader, a direct conversion passive micro-mixer combined with a 180 degrees ring hybrid coupler is realized to operate over the unlicensed 60 GHz frequency band. This is followed by a low phase error Rotman lens combined with a patch antenna array in each output port to support beam steering and increasing the communication range. Experimental measurements on a fabricated 3-bit chipless tag show that the tag can backscatter a unique identification code to an RFID interrogator

セキュアRFIDタグチップの設計論

In this thesis, we focus on radio frequency identification (RFID) tag. We design, implement, and evaluate hardware performance of a secure tag that runs the authentication protocol based on cryptographic algorithms. The cryptographic algorithm and the pseudorandom number generator are required to be implemented in the tag. To realize the secure tag, we tackle the following four steps: (A) decision of hardware architecture for the authentication protocol, (B) selection of the cryptographic algorithm, (C) establishment of a pseudorandom number generating method, and (D) implementation and performance evaluation of a silicon chip on an RFID system.(A) The cryptographic algorithm and the pseudorandom number generator are repeatedly called for each authentication. Therefore, the impact of the time needed for the cryptographic processes on the hardware performance of the tag can be large. While low-area requirements have been mainly discussed in the previous studies, it is needed to discuss the hardware architecture for the authentication protocol from the viewpoint of the operating time. In this thesis, in order to decide the hardware architecture, we evaluate hardware performance in the sense of the operating time. As a result, the parallel architecture is suitable for hash functions that are widely used for tag authentication protocols.(B) A lot of cryptographic algorithms have been developed and hardware performance of the algorithms have been evaluated on different conditions. However, as the evaluation results depend on the conditions, it is hard to compare the previous results. In addition, the interface of the cryptographic circuits has not been paid attention. In this thesis, in order to select a cryptographic algorithm, we design the interface of the cryptographic circuits to meet with the tag, and evaluate hardware performance of the circuits on the same condition. As a result, the lightweight hash function SPONGENT-160 achieves well-balanced hardware performance.(C) Implementation of a pseudorandom number generator based on the performance evaluation results on (B) can be a method to generate pseudorandom number on the tag. On the other hand, as the cryptographic algorithm and the pseudorandom number generator are not used simultaneously on the authentication protocol. Therefore, if the cryptographic circuit could be used for pseudorandom number generation, the hardware resource on the tag can be exploited efficiently. In this thesis, we propose a pseudorandom number generating method using a hash function that is a cryptographic component of the authentication protocol. Through the evaluation of our proposed method, we establish a lightweight pseudorandom number generating method for the tag.(D) Tag authentication protocols using a cryptographic algorithm have been developed in the previous studies. However, hardware implementation and performance evaluation of a tag, which runs authentication processes, have not been studied. In this thesis, we design and do a single chip implementation of an analog front-end block and a digital processing block including the results on (A), (B), and (C). Then, we evaluate hardware performance of the tag. As a result, we show that a tag, which runs the authentication protocol based on cryptographic algorithms, is feasible.電気通信大学201

Non-linear shunt regulator based on a PWM RF power detector for RFID applications

Radio Frequency Identification (RFID) is utilized in a variety of applications, includ ing tagging animals and objects to make their identification (ID) easier to read and man age, similar to a bar code or QR code. In this regard, the goal of this research is to improve RFID transponder power regulation in order to increase reader distance. This thesis de scribes a non-linear shunt regulator that employs a Radio Frequency (RF) power detector based on the Pulse Width Modulation (PWM) technique to aim magnetically coupled RFID transponders. A quick voltage-clamp loop and a slow-accurate power detector loop are used in the proposed regulator architecture. The first loop ensures over-voltage pro tection, while the second loop gradually corrects the first loop’s imprecision based on the measured input power. To contextualize the issues and improvements of the new design, the state-of-the-art in RFID power management and RF power detector are covered first. The new architecture is specified after theoretical development, electrical simulations, and the design of the new architecture is implemented. The entire regulator design was prototyped as part of a commercial low-frequency (134 kHz) RFID transponder in a 180 nm CMOS process. The regulator deal with a sinusoidal voltage at its input generated by the LC tank that extracts energy from the reader to supply its circuitry. The use of a 3.3V standard process for the analog circuitry in order to decrease the fabrication cost by not using the high voltage module (5 V for example) complicates the system design. Even though the proposed solution aims to regulate the input voltage precisely at 3.6 V maximum, the maximum voltage supported by 3.3 V standard module using two feedback is achieved. The total RFID transponder area of 870x870 µm² was obtained, with 130x230 µm² related to the regulator circuit area only. Both resonant and supply capacitors are imple mented on the chip. The complete system consumes a maximum current of 4.5 µA, over a wide RF input power range that is modulated by the distance between the reader and the transponder. As the power detector corrects the imprecision of the shunt regulator com posed by simple diodes due to its process, voltage and temperature (PVT), the transponder performance was measured with and without the shunt regulator enabled. Results show an improvement of 16.7 % in the communication distance between the transponder and the reader.Identificação por Rádio Frequência (RFID) é usada em muitas aplicações, colocando etiquetas eletrônicas em animais e objetos para facilitar a leitura a fim de melhorar o gerenciamento destes. Nesse contexto, essa dissertação tem como objetivo melhorar a regulação de potência em chips de RFID a fim de aumentar a distância de leitura. Essa dissertação apresenta um nova arquitetura de regulador paralelo, não linear, que usa um detector de potência de Rádio Frequência (RF) baseado em uma técnica de modulação de pulso (PWM) para aplicação de RFID que usam o princípio de comunicação por acopla mento magnético. A arquitetura de regulador proposto é composta de duas realimen tações: uma realimentação usa um limitador de tensão rápido e a outra usa um detector de potência lento porém preciso. O primeiro garante a proteção contra sobre tensão e o segundo corrige a imprecisão do primeiro de acordo com a potência do sinal de entrada. Primeiramente, o estado da arte em regulação de sitemas de RFID bem como em detectores de potência RF são feitos para contextualizar os problemas e melhorias da nova arquitetura. Um desenvolvimento teórico seguido por simulações elétricas e o projeto do circuito da nova arquitetura de regulador paralelo são abordadas em detalhes. A circuito foi implementado em um processo CMOS de 180 nm como parte de um Chip de RFID de baixa frequência (134 kHz). O regulador lida com uma tensão senoidal (134 kHz) na sua entrada, gerada por um tanque LC que extrai energia provinda do leitor e que é usada alimentar todo o chip. Devido ao uso de um processo padrão 3.3 V CMOS para implementação do circuitos analógicos a fim de diminuir o custo de fabricação com o não uso do modulo de alta tensão (Ex. 5 V), impondo dificuldades no projeto do sistema, mesmo assim a solução proposta regula a tensão de entrada do chip em 3.6 V, máxima suportada pela tecnologia, com o uso das duas malhas de realimentação. A área total do Chip de RFID é de 870x870 µm², com 130x230 µm² para apenas o circuito de regulação. Os capacitores de ressonância e de alimentação foram integrados no Chip. O sistema completo consome 4.5 µA, sobre uma ampla gama de potência de entrada que é modulada pela distância entre o leitor e a tag. Como o detector de potência corrige a imprecisão do limitador de tensão composto de diodos devido a variação em processo, tensão e temperatura (PVT), a distância de leitura foi medida com e sem o detector de potência habilitado. Os resultados mostraram uma melhoria de 16.7 % na distância de comunicação

A Flexible Ultralight Hardware Security Module for EPC RFID Tags

Due to the rapid growth of using Internet of Things (IoT) devices in daily life, the need to achieve an acceptable level of security and privacy for these devices is rising. Security risks may include privacy threats like gaining sensitive information from a device, and authentication problems from counterfeit or cloned devices. It is more challenging to add security features to extremely constrained devices, such as passive Electronic Product Code (EPC) Radio Frequency Identification (RFID) tags, compared to devices that have more computational and storage capabilities. EPC RFID tags are simple and low-cost electronic circuits that are commonly used in supply chains, retail stores, and other applications to identify physical objects. Most tags today are simple "license plates" that just identify the object they are attached to and have minimal security. Due to the security risks of new applications, there is an important need to implement secure RFID tags. Examples of the security risks for these applications include unauthorized physical tracking and inventorying of tags. The current commercial RFID tag designs use specialised hardware circuits approach. This approach can achieve the lowest area and power consumption; however, it lacks flexibility. This thesis presents an optimized application-specific instruction set architecture (ISA) for an ultralight Hardware Security Module (HSM). HSMs are computing devices that protect cryptographic keys and operations for a device. The HSM combines all security-related functions for passive RFID tag. The goal of this research is to demonstrate that using an application-specific instruction set processor (ASIP) architecture for ultralight HSMs provides benefits in terms of trade-offs between flexibility, extensibility, and efficiency. Our novel application specific instruction-set architecture allows flexibility on many design levels and achieves acceptable security level for passive EPC RFID tag. Our solution moves a major design effort from hardware to software, which largely reduces the final unit cost. Our ASIP processor can be implemented with 4,662 gate equivalent units (GEs) for 65 nm CMOS technology excluding cryptographic units and memories. We integrated and analysed four cryptographic modules: AES and Simeck block ciphers, WG-5 stream cipher, and ACE authenticated encryption module. Our HSM achieves very good efficiencies for both block and stream ciphers. Specifically for the AES cipher, we improve over a previous programmable AES implementation result by 32x. We increase performance dramatically and increase/decrease area by 17.97/17.14% respectively. These results fulfill the requirements of extremely constrained devices and allow the inclusion of cryptographic units into the datapath of our ASIP processor

Next-generation IoT devices: sustainable eco-friendly manufacturing, energy harvesting, and wireless connectivity

This invited paper presents potential solutions for tackling some of the main underlying challenges toward developing sustainable Internet-of-things (IoT) devices with a focus on eco-friendly manufacturing, sustainable powering, and wireless connectivity for next-generation IoT devices. The diverse applications of IoT systems, such as smart cities, wearable devices, self-driving cars, and industrial automation, are driving up the number of IoT systems at an unprecedented rate. In recent years, the rapidly-increasing number of IoT devices and the diverse application-specific system requirements have resulted in a paradigm shift in manufacturing processes, powering methods, and wireless connectivity solutions. The traditional cloud-centering IoT systems are moving toward distributed intelligence schemes that impose strict requirements on IoT devices, e.g., operating range, latency, and reliability. In this article, we provide an overview of hardware-related research trends and application use cases of emerging IoT systems and highlight the enabling technologies of next-generation IoT. We review eco-friendly manufacturing for next-generation IoT devices, present alternative biodegradable and eco-friendly options to replace existing materials, and discuss sustainable powering IoT devices by exploiting energy harvesting and wireless power transfer. Finally, we present (ultra-)low-power wireless connectivity solutions that meet the stringent energy efficiency and data rate requirements of future IoT systems that are compatible with a batteryless operation

UHF Energy Harvesting and Power Management

As we are entering the era of Internet of Things (i.e. IoT), the physical devices become increasingly connected with each other than ever before. The connection between devices is achieved through wireless communication schemes, which unfortunately consume a significant amount of energy. This is undesirable for devices which are not directly connected to power. This is because these devices will essentially carry batteries to supply the needed energy for these operations and the batteries will eventually be depleted. This motivates the need to operate these devices off harvested energy. UHF energy harvesting, as an enabling technology for the UHF RFID, stands out amongst other energy harvesting approaches as it does not heavily rely on the natural surrounding environment and also offers a very good wireless operating range from its radiating energy source. Unlike the RFID, the power consumption and the operational range requirement of these IoT devices can vary significantly. Thus, the design of the RF energy harvesting front-end and the power management need to be re-thought for specific applications. To that end, in this thesis, discussions mainly evolve around the design of UHF energy harvesters and their associated power management units using lower power analog approaches. First, we present the background of the low power UHF energy harvesting, specially threshold-compensated rectifiers will be presented as a key technology in this area and this will be used as a build practical harvester for the UHF RFID application. Secondly, key issues with the threshold compensation will be identified and this is exploited either (i) to improve the dynamic power conversion efficiency of the harvester, (ii) to improve dynamic settling behaviour of the harvester. To exploit the ”left-over” harvested energy, an intelligent integrated power management solution has been proposed. Finally, the charge-burst approach is exploited to implement an energy harvester with -40 dBm input power sensitivity.Thesis (Ph.D.) -- University of Adelaide, School of Electrical & Electronic Engineering, 201