Built-in self test of RF subsystems

textWith the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs.Electrical and Computer Engineerin

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

Advanced modelling of the Planck-LFI radiometers

The Low Frequency Instrument (LFI) is a radiometer array covering the 30-70 GHz spectral range on-board the ESA Planck satellite, launched on May 14th, 2009 to observe the cosmic microwave background (CMB) with unprecedented precision. In this paper we describe the development and validation of a software model of the LFI pseudo-correlation receivers which enables to reproduce and predict all the main system parameters of interest as measured at each of the 44 LFI detectors. These include system total gain, noise temperature, band-pass response, non-linear response. The LFI Advanced RF Model (LARFM) has been constructed by using commercial software tools and data of each radiometer component as measured at single unit level. The LARFM has been successfully used to reproduce the LFI behavior observed during the LFI ground-test campaign. The model is an essential element in the database of LFI data processing center and will be available for any detailed study of radiometer behaviour during the survey.Comment: 21 pages, 15 figures, this paper is part of the Prelaunch status LFI papers published on JINST: http://www.iop.org/EJ/journal/-page=extra.proc5/jins

The PreAmplifier ShAper for the ALICE TPC-Detector

In this paper the PreAmplifier ShAper (PASA) for the Time Projection Chamber (TPC) of the ALICE experiment at LHC is presented. The ALICE TPC PASA is an ASIC that integrates 16 identical channels, each consisting of Charge Sensitive Amplifiers (CSA) followed by a Pole-Zero network, self-adaptive bias network, two second-order bridged-T filters, two non-inverting level shifters and a start-up circuit. The circuit is optimized for a detector capacitance of 18-25 pF. For an input capacitance of 25 pF, the PASA features a conversion gain of 12.74 mV/fC, a peaking time of 160 ns, a FWHM of 190 ns, a power consumption of 11.65 mW/ch and an equivalent noise charge of 244e + 17e/pF. The circuit recovers smoothly to the baseline in about 600 ns. An integral non-linearity of 0.19% with an output swing of about 2.1 V is also achieved. The total area of the chip is 18 mm$^2$ and is implemented in AMS's C35B3C1 0.35 micron CMOS technology. Detailed characterization test were performed on about 48000 PASA circuits before mounting them on the ALICE TPC front-end cards. After more than two years of operation of the ALICE TPC with p-p and Pb-Pb collisions, the PASA has demonstrated to fulfill all requirements

AMiBA: Broadband Heterodyne CMB Interferometry

The Y. T. Lee Array for Microwave Background (AMiBA) has reported the first science results on the detection of galaxy clusters via the Sunyaev Zel'dovich effect. The science objectives required small reflectors in order to sample large scale structures (20') while interferometry provided modest resolutions (2'). With these constraints, we designed for the best sensitivity by utilizing the maximum possible continuum bandwidth matched to the atmospheric window at 86-102GHz, with dual polarizations. A novel wide-band analog correlator was designed that is easily expandable for more interferometer elements. MMIC technology was used throughout as much as possible in order to miniaturize the components and to enhance mass production. These designs will find application in other upcoming astronomy projects. AMiBA is now in operations since 2006, and we are in the process to expand the array from 7 to 13 elements.Comment: 10 pages, 6 figures, ApJ in press; a version with high resolution figures available at http://www.asiaa.sinica.edu.tw/~keiichi/upfiles/AMiBA7/mtc_highreso.pd

An Analogue Front-End Test-Bed for Software Defined Radio

A Software Defined Radio (SDR) is a radio receiver and/or transmitter, whose characteristics can to a large extent be defined by software. Thus, an SDR can receive and/or transmit a wide variety of signals, supporting many different standards. In our research, we currently focus on a demonstrator that is able to receive both Bluetooth and HiperLAN/2. This helps us to identify problems associated with SDR, and will provide a test-bed for possible solutions to these problems. The two standards differ significantly in characteristics like frequency band, signal bandwidth and modulation type. Combining two different standards in one receiver appears to pose new design challenges. For example, in the wide frequency range that we want to receive, many strong signals\ud may exist. This leads to severe linearity requirements for wideband receivers. This paper describes some receiver architectures. One\ud design has been selected. This receiver has been built, and some measurement results are included

An Analogue Front-End Architecture for Software Defined Radio

A Software Defined Radio (SDR) is a radio receiver and/or transmitter, whose characteristics can to a large extent be defined by software. Thus, an SDR can receive and/or transmit a wide variety of signals, supporting many different standards. In our research, we currently focus on a demonstrator that is able to receive both Bluetooth and HiperLAN/2. This helps us to identify problems associated with SDR, and will provide a test-bed for possible solutions to these problems. The two standards differ significantly in characteristics like frequency band, signal bandwidth and modulation type. Combining two different standards in one receiver appears to pose new design challenges. For example, in the wide frequency range that we want to receive, many strong signals\ud may exist. This leads to severe linearity requirements for wideband receivers. This paper describes some receiver architectures. One\ud design has been selected. This receiver has been built, and some measurement results are included

Reconfiguration based built-in self-test for analogue front-end circuits

Previous work has shown that it is feasible to implement a fully digital test evaluation function to realise partial self-test on an automatic gain control circuit (AGC). This paper extends the technique to INL, DNL, offset & gain error testing of analogue to digital converters (ADC's). It also shows how the same function can be used to test an AGC / ADC pair. An extension to full self-test is also proposed by the on-chip generation of input stimuli through reconfiguration of existing functions

Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio

A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation