Cost modelling and concurrent engineering for testable design

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.As integrated circuits and printed circuit boards increase in complexity, testing becomes a major cost factor of the design and production of the complex devices. Testability has to be considered during the design of complex electronic systems, and automatic test systems have to be used in order to facilitate the test. This fact is now widely accepted in industry. Both design for testability and the usage of automatic test systems aim at reducing the cost of production testing or, sometimes, making it possible at all. Many design for testability methods and test systems are available which can be configured into a production test strategy, in order to achieve high quality of the final product. The designer has to select from the various options for creating a test strategy, by maximising the quality and minimising the total cost for the electronic system. This thesis presents a methodology for test strategy generation which is based on consideration of the economics during the life cycle of the electronic system. This methodology is a concurrent engineering approach which takes into account all effects of a test strategy on the electronic system during its life cycle by evaluating its related cost. This objective methodology is used in an original test strategy planning advisory system, which allows for test strategy planning for VLSI circuits as well as for digital electronic systems. The cost models which are used for evaluating the economics of test strategies are described in detail and the test strategy planning system is presented. A methodology for making decisions which are based on estimated costing data is presented. Results of using the cost models and the test strategy planning system for evaluating the economics of test strategies for selected industrial designs are presented

NASA patent abstracts bibliography: A continuing bibliography. Section 2: Indexes (supplement 12)

For abstract, see N78-27983

NASA patent abstracts bibliography: A continuing bibliography. Section 2: Indexes (supplement 13)

This issue of the Index Section contains entries for 3386 patent and application for patent citations covering the period May 1969 through June 1978. The Index Section contains five indexes --- subject, inventor, source, number, and accession number

NASA patent abstracts bibliography: A continuing bibliography. Section 2: Indexes (supplement 14)

This issue of the Index Section contains entries for 3512 patent and applications for patent citations covering the period May 1969 through December 1978. The Index Section contains five indexes --- subject, inventor, source, number, and accession number

Microchip test environment

With the ever-increasing demand for more powerful chips, it is necessary to integrate multiple circuits inside a chip. These chips are called a system on a chip (SoC). Even though SoCs integrate more and more functionality inside a single chip they still require a printed circuit board which at least provides power and input and output connectors. Tampere University together with multiple companies started SoC Hub project. The goal of this project is to develop a system on a chip and increase Finnish system on a chip design expertise. The target is to develop one system on a chip in a year with three SoCs in total. The goal of this master’s thesis is to design a printed circuit board that can be used to test the first iteration of the SoC. Printed circuit boards which are designed for testing have three main functions: provide power, provide input and output connectors and their circuitry, and to make testing as easy as possible. This system on a chip requires three different power rails, which must be turned on and off in a sequence and they must also be monitored in case of a fault. For this purpose, a power management system was developed in which a microcontroller monitors and controls the power rails. On the printed circuit board most of the input and output connectors use pin headers. The pin headers make testing easy as most signals are available in simple pin headers. Some signals also have more specialized connectors such as an SD card socket. Testability was also a major concern when deciding the stack up of the printed circuit board. All signals are routed on the outer layers so that they are easily available and can be slightly modified if needed. Some difficulties were also faced during the design process of the printed circuit board. Of these the biggest was the global chip shortage, because of which most of the chips that could have been used were not available. Due to chip shortage most of the chips had to be changed during the design phase and some chips had to be replaced by alternative means like using ready-made modules. Despite these problems the printed circuit boards were designed and manufactured before the SoCs arrived. The printed circuit boards were tested to be functional after which they could be used for their intended purpose of testing the SoCs

Development of data acquisition and control facilities for the optimization of drive line efficiency

Call number: LD2668 .T4 1986 F86Master of ScienceMechanical and Nuclear Engineerin

NASA patent abstracts bibliography: A continuing bibliography. Section 2: Indexes (supplement 10)

Abstracts for 3089 patents and applications for patent entered in the NASA scientific and information system for the period covering May 1969 through December 1976 are indexed by subject, inventor, source, NASA case or U.S. patent number, and accession number in the NASA system

NASA patent abstracts bibliography: A continuing bibliography. Section 2: Indexes (supplement 06)

For abstract, see N75-20149

NASA patent abstracts bibliography: A continuing bibliography. Section 2: Indexes (supplement 05)

For abstract, see N75-13677

Theory and design of reliable spacecraft data systems

Theory and techniques applicable to design, analysis, and fault diagnosis of reliable spacecraft data system