EFFICIENT QUANTIZATION PARAMETER ESTIMATION IN HEVC BASED ON ρ-DOMAIN

International audienceThis paper proposes a quantization parameter estimation algorithm for HEVC CTU rate control. Several methods were proposed, mostly based on Lagrangian optimization combined with Laplacian distribution for transformed coeffi-cients. These methods are accurate but increase the encoder complexity. This paper provides an innovative reduced com-plexity algorithm based on a ρ-domain rate model. Indeed, for each CTU, the algorithm predicts encoding parameters based on co-located CTU. By combining it with Laplacian distri-bution for transformed coefficients, we obtain the dead-zone boundary for quantization and the related quantization pa-rameter. Experiments in the HEVC HM Reference Software show a good accuracy with only a 3% average bitrate error and no PSNR deterioration for random-access configuration

A Decoding-Complexity and Rate-Controlled Video-Coding Algorithm for HEVC

Video playback on mobile consumer electronic (CE) devices is plagued by fluctuations in the network bandwidth and by limitations in processing and energy availability at the individual devices. Seen as a potential solution, the state-of-the-art adaptive streaming mechanisms address the first aspect, yet the efficient control of the decoding-complexity and the energy use when decoding the video remain unaddressed. The quality of experience (QoE) of the end-users’ experiences, however, depends on the capability to adapt the bit streams to both these constraints (i.e., network bandwidth and device’s energy availability). As a solution, this paper proposes an encoding framework that is capable of generating video bit streams with arbitrary bit rates and decoding-complexity levels using a decoding-complexity–rate–distortion model. The proposed algorithm allocates rate and decoding-complexity levels across frames and coding tree units (CTUs) and adaptively derives the CTU-level coding parameters to achieve their imposed targets with minimal distortion. The experimental results reveal that the proposed algorithm can achieve the target bit rate and the decoding-complexity with 0.4% and 1.78% average errors, respectively, for multiple bit rate and decoding-complexity levels. The proposed algorithm also demonstrates a stable frame-wise rate and decoding-complexity control capability when achieving a decoding-complexity reduction of 10.11 (%/dB). The resultant decoding-complexity reduction translates into an overall energy-consumption reduction of up to 10.52 (%/dB) for a 1 dB peak signal-to-noise ratio (PSNR) quality loss compared to the HM 16.0 encoded bit streams

Content-Split Block Search Algorithm Based High Efficiency Video Coding

690-693In this paper, the video streaming generation in H.265 using novel technique based on content split block (CSB) search algorithm is presented. The proposed algorithm exploits the Inter and Intra prediction through motion estimation and compensation (IPME) encoded to use four different QPs: 22, 27, 32, and 37, during the redundancy analysis in order to improve the quality of video frame encoded. The proposed algorithm exhibits the useful property of block structure based on content-tree representation for each and every frame to IPME coded without affecting either the bit rate of video stream and perceptual quality of the video frame. The proposed Search algorithm improves the visual quality of coded video frame and reduces the blocking artefacts of video frame passed through multi-stages of H.265

Hierarchical-p reference picture selection based error resilient video coding framework for high efficiency video coding transmission applications

In this paper, a new reference picture selection (RPS) is proposed for a high efficiency video coding (HEVC) framework. In recent studies, HEVC has been shown to be sensitive to packet error which is unavoidable in transmission applications especially for wireless networks. RPS is an effective error resilient technique for video transmission systems where a feedback channel with short round trip delay time is available. However, its procedure cannot directly apply to the HEVC framework and thus this paper expands it. In RPS, error propagation can still happen during round trip delay time. To alleviate the effect of error propagation for better quality, the proposed algorithm considers both the RPS technique and the region-based intra mode selection method by using some novel features of HEVC. Experimental results demonstrate that the proposed method outperforms the hierarchical-P RPS algorithm in terms of PSNR and other metrics. The average PSNR improvement of the proposed algorithm over the reference algorithm under 10% packet error rate is 1.56 dB for 1080p sequences, 2.32 dB for 720p sequences and 1.01 dB for wide video graphics array (WVGA) sequences, respectively. The performance of proposed method is also tested for applications where feedback information is not available. The proposed method shows noticeable improvement for video sequences that contain low or moderate level of motions

Efficient HEVC-based video adaptation using transcoding

In a video transmission system, it is important to take into account the great diversity of the network/end-user constraints. On the one hand, video content is typically streamed over a network that is characterized by different bandwidth capacities. In many cases, the bandwidth is insufficient to transfer the video at its original quality. On the other hand, a single video is often played by multiple devices like PCs, laptops, and cell phones. Obviously, a single video would not satisfy their different constraints. These diversities of the network and devices capacity lead to the need for video adaptation techniques, e.g., a reduction of the bit rate or spatial resolution. Video transcoding, which modifies a property of the video without the change of the coding format, has been well-known as an efficient adaptation solution. However, this approach comes along with a high computational complexity, resulting in huge energy consumption in the network and possibly network latency. This presentation provides several optimization strategies for the transcoding process of HEVC (the latest High Efficiency Video Coding standard) video streams. First, the computational complexity of a bit rate transcoder (transrater) is reduced. We proposed several techniques to speed-up the encoder of a transrater, notably a machine-learning-based approach and a novel coding-mode evaluation strategy have been proposed. Moreover, the motion estimation process of the encoder has been optimized with the use of decision theory and the proposed fast search patterns. Second, the issues and challenges of a spatial transcoder have been solved by using machine-learning algorithms. Thanks to their great performance, the proposed techniques are expected to significantly help HEVC gain popularity in a wide range of modern multimedia applications

Studying Rate Control Methods for UHDTV Delivery Using HEVC

Since the early video coding standardisation efforts, rate control has been considered essential for almost any application, and has therefore been extensively studied. With the advent of improved video coding standards, such as the current stateof-the-art High Efficiency Video Coding (HEVC) standard, and the introduction of advanced flexible coding tools, previous Rate-Distortion (RD) models used for rate control have become obsolete. To address this issue, some rate control methods have been recently proposed specifically for HEVC which introduce many useful features, such as a robust correspondence between the rate and Lagrange multiplier . However, when applying these rate control methods on sequences in the new Ultra High Definition Television (UHDTV) format, degraded coding performance was observed. In this paper, an analysis of the state-of-the-art HEVC rate control method was performed and two directions for its improvement were evaluated. These improvements target frame-level bit-allocation and model parameter initialisation. When compared to the rate control method implemented in the HEVC reference software, these improvements result in reduced BDrate losses of 3:1% and 2:1%, versus the 8:8% provided by the reference algorithm. Moreover, the proposed improvements improve the accuracy in hitting the target bit-rate./p

HEVC-videokoodekin intra-ennustuksen toteutus FPGA-piireille C-kielestä syntesoimalla

High Efficiency Video Coding (HEVC) is the latest video coding standard in video compression. With HEVC, it is possible to compress the video with half the bitrate compared to the previous video coding standard, Advanced Video Coding (AVC), with the same video quality. Now even, the complexity of the encoder is significantly larger. As designs become more and more complex, traditional hardware (HW) description languages (HDLs), such as Very High Speed Integrated Circuit Hardware Description Language (VHDL) or Verilog, can not be used to present the designs without increasing effort. The solution for this is a higher abstraction language for describing HW. High-Level Synthesis (HLS) is a way of using a programming language like C or C++ to describe the HW and automatically generating the HDL from it. This makes the code easier to understand and decreases the time used for implementing the design. This Thesis uses Catapult-C to create an HLS-based implementation of HEVC intra prediction for a Field Programmable Gate Array (FPGA). The HEVC encoder used in this Thesis is open source Kvazaar which has been developed at Tampere University of Technology. The objective is to implement an intra prediction accelerator faster than implementing it with register-transfer level (RTL) using VHDL or Verilog and still get comparable area and performance. This Thesis presents six development versions of the intra prediction accelerator. The complexity of the accelerator grows gradually, as more features were added to it. The final version is able to perform the intra prediction, mode cost computation and mode decision for Full HD video at 24.5 fps using 11 662 adaptive logic modules (ALMs) on an Altera Cyclone V FPGA. This Thesis presents the benefits of Catapult-C and HLS. The implementation results were comparable to hand coded RTL but achieved with a fraction of the estimated time for a VHDL implementation. As a rough estimate, if something takes a month to implement in VHDL, it takes a week with HLS. The biggest gain with HLS is the fast process of changes. Only the C implementation needs to change. The testbench and the RTL-code are generated automatically

Full RDO를 사용하는 HEVC 하드웨어를 위한 Rate Control 알고리듬의 개선과 구현

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. 채수익.HM 인코더에서 적용된 coding tree unit (CTU) 수준의 rate control을 적용하면, rate control을 적용하지 않았을 경우에 비해서 코딩 효율이 나빠져 Bjøntegaard-delta rate (BD rate)가 약 4.14 % 증가한다. 그리고 HM 인코더에서는 rate control 알고리듬이 floating point로 구현되어 있어 HW 구현에 적합하지 않다. 그래서 이 논문은 HEVC의 reference SW인 HM 인코더에 적용되어 있는 rate control 알고리듬의 코딩 효율을 개선한 내용과, HW 구현에 적합하게 수정하고 내용을 설명한 후에, 수정된 rate control 알고리듬의 HW 구현에 대해서 기술한다. 이 논문의 기여는 picture 수준의 bit 할당 방법 개선, HW 구현에 적합한 full RD cost의 사용, log를 취한 log R-log λ model의 도입, 그리고 개선한 rate control 알고리듬의 HW 구현이다. HM 인코더의 rate control에서 picture 수준의 bit 할당은 이미지 시퀀스에 따라서 이미지 후반부에 bit rate이 부족하여 picture의 peak signal-to-noise ratio (PSNR)이 급격히 떨어지는 현상을 보인다. 이 현상을 완화하기 위하여 전체 이미지 시퀀스에서 target bit 할당을 이미지 초반부에 bit을 조금 덜 할당하여 이미지 시퀀스 후반부에 좀 더 bit을 할당하여 이미지 시퀀스 후반에 PSNR이 떨어지는 현상을 완화시키도록 picture 수준 bit 할당을 위한 수정된 알고리듬을 제안한다. 그리고 transform & full RDO & reconstruction을 위한 pipeline stage에서 full RD cost를 이용한 rate distortion optimization (RDO)을 사용한다고 가정한다. 이 pipeline stage에서 full RD cost 계산하는 HW 구현을 위하여 두 가지 기법을 사용했다. 첫째로 rate control의 코딩 효율을 높이기 위해서, CTU별 λ가 아닌 picture의 평균 λ를 이용하여 인코딩을 수행하였다. 둘째로 full RD cost 계산의 HW 복잡도를 줄이기 위해서 quantization step size (Qstep)의 제곱으로 나눈 normalized full RD cost를 사용하여 full RD cost의 dynamic range를 크게 줄였다. HM 인코더에서 rate control의 R-λ model은 floating point로 구현이 되어 있고 지수 연산을 이용하기 때문에 HW 구현에 적합하지 않다. 그래서 R-λ model을, 선형 연산을 이용할 수 있고 HW 구현에 적합하도록, log를 취하여 log R-log λ model로 변형하였다. HM 인코더에서 사용하는 R-D model인 hyperbolic model의 parameter update할 때 log를 취한 model parameter의 update의 근사이기 때문에 log R-log λ model을 이용하였을 때 코딩 효율이 오히려 조금 좋아졌다. 그리고 rate과 관련된 변수들의 log domain과 real domain에서의 값 변환을 위해서 look-up table (LUT)을 이용한 log2와 anti-log2를 구현하였다. 또한 나눗셈 연산도 LUT을 이용하여 HW의 복잡도를 줄여 구현하였다. 제안하는 rate control 방법의 효용성을 5개의 1080p 이미지 시퀀스 Kimono, ParkScene, Cactus, BasketballDrive, BQTerrace에 대하여 인코딩 결과로 판단했다. 인코딩 환경은 common test condition의 random access (RA) configuration으로 TU split을 지원하지 않도록 하여 maximum TU depth를 1로 설정하였다. Rate control의 target rate은 rate control을 사용하지 않고 QP 22, 27, 32, 37로 인코딩한 경우에 발생한 rate들로 정하였다. 이 조건에서 개선한 rate control 알고리듬은 HM 인코더에 적용된 CTU-level rate control의 Y-BD rate 4.14 %를 1.99 %로 감소시킨다. 그리고 후반에 PSNR이 떨어지는 현상을 줄여서 minimum PSNR을 평균 0.11 dB 향상 시켰고 특히 ParkScene 이미지 시퀀스에서는 최대 1.58 dB까지 향상시켰다. 제안한 rate control algorithm을 HW로 GOP, picture, CTU level을 모두 지원하도록 구현했는데, 그 전체 복잡도는 27.5 kgate이고 추가로 32 KB의 메모리가 필요하다. Rate control의 수행에 필요한 cycle budget은 CTU당 4 cycle로 4K 30 fps를 400 MHz에 수행한다고 하였을 경우에 0.06 %의 overhead에 해당하며 전체 인코딩 과정의 영향을 거의 주지 않는 수준이다.제 1 장 서 론 1 1.1 연구의 배경 2 1.2 관련 연구 7 1.3 전체 논문의 구성 12 제 2 장 HEVC HW 인코더의 pipeline 구성 13 2.1 가정하는 HEVC HW 인코더의 pipeline 구성 13 2.2 가정하는 HW 구조의 코딩 효율 저하 17 2.3 Full RD cost 예측기 HW 구현의 개요 20 제 3 장 HEVC의 CTU-level Rate control의 알고리듬 설명 23 3.1 HM 인코더의 CTU-level rate control 전체 과정 23 3.2 Target bit allocation 25 3.3 λ and QP calculation 32 3.4 Encoding 35 3.5 Model parameter update 35 제 4 장 HEVC의 CTU-level Rate control의 알고리듬의 코딩 효율 개선 39 4.1 Rate control의 실험 환경과 HM 인코더의 실험 결과 39 4.2 Bit saving을 이용한 Picture-level bit allocation 43 4.3 Picture의 평균 λ를 이용한 rate control의 코딩 효율 개선 50 4.4 Full RDO에서 이용하는 normalized RD cost 51 제 5 장 HEVC의 CTU-level Rate control의 HW 구현 57 5.1 HW 구현을 위한 log를 취한 log R-log λ model 58 5.2 HW 구현을 위한 GOP의 picture별 target rate 계산 방법 62 5.3 HW 구현을 위한 model parameter update 68 5.4 Rate control의 HW 구현을 위한 fixed point 연산과 LUT 사용 70 5.5 Rate control의 HW 구현과 HW 인코더에서의 rate control의 동작 75 제 6 장 결 론 81 참고 문헌 83 Abstract 87Docto