Multilevel Power Estimation Of VLSI Circuits Using Efficient Algorithms

New and complex systems are being implemented using highly advanced Electronic Design Automation (EDA) tools. As the complexity increases day by day, the dissipation of power has emerged as one of the very important design constraints. Now low power designs are not only used in small size applications like cell phones and handheld devices but also in high-performance computing applications. Embedded memories have been used extensively in modern SOC designs. In order to estimate the power consumption of the entire design correctly, an accurate memory power model is needed. However, the memory power model commonly used in commercial EDA tools is too simple to estimate the power consumption accurately. For complex digital circuits, building their power models is a popular approach to estimate their power consumption without detailed circuit information. In the literature, most of power models are built with lookup tables. However, building the power models with lookup tables may become infeasible for large circuits because the table size would increase exponentially to meet the accuracy requirement. This thesis involves two parts. In first part it uses the Synopsys power measurement tools together with the use of synthesis and extraction tools to determine power consumed by various macros at different levels of abstraction including the Register Transfer Level (RTL), the gate and the transistor level. In general, it can be concluded that as the level of abstraction goes down the accuracy of power measurement increases depending on the tool used. In second part a novel power modeling approach for complex circuits by using neural networks to learn the relationship between power dissipation and input/output characteristic vector during simulation has been developed. Our neural power model has very low complexity such that this power model can be used for complex circuits. Using such a simple structure, the neural power models can still have high accuracy because they can automatically consider the non-linear power distributions. Unlike the power characterization process in traditional approaches, our characterization process is very simple and straightforward. More importantly, using the neural power model for power estimation does not require any transistor-level or gate-level description of the circuits. The experimental results have shown that the estimations are accurate and efficient for different test sequences with wide range of input distributions

A novel maximal-length sequence synchronisation network

Spread Spectrum has become a popular digital modulation scheme in recent years. The advantages the scheme offers, at the expense of bandwidth, make it attractive in a multitude of commercial applications. The most common method, and the one of interest in this thesis, of generating Spread Spectrum is multiplying the data waveform by a wideband, digitally generated waveform. This is referred to as Direct Sequence Spread Spectrum. The characteristics of Spread Spectrum systems are determined by the spreading waveform. A common group of spreading waveforms, and the ones dealt with in this text, are the maximal-length sequences. These are a class of pseudorandom waveforms. Their properties include a two valued autocorrelation function with its maximum value at no code-phase offset. This allows for multiple access to a single resource and the suppression of multi-path interference as adjacent codes have little effect on each other. This same property requires that the receiver must accurately align its replica of the spreading waveform to the transmitted waveform in order to despread the received waveform and demodulate the data. Common methods of synchronisation use a two pronged solution. Firstly the correct code phase is determined. This is referred to as code acquisition. Secondly the clocking frequency of the received waveform must be resolved in order to precisely align the two sequences. This is referred to as code tracking. Receivers therefore tend to be complex and expensive. This thesis involved the investigation of two pseudo-noise synchronisation networks proposed by J .G. van de Groenendaal. These networks offered both code acquisition and tracking in a single robust loop. The investigation, done in co-operation with J..G. van de Groenendaal, persued two avenues. Firstly the loops were simulated. This method allows for the easy alteration of system parameters. Valuable insight into the loop dynamics can thus be gained. Secondly the loops were built on the bench. This allows for the practical confirmation of the results of the simulation. Both synchronisation loops were based on variations of the maximal likelihood phase detector. This phase detector is formed by taking the product of the first derivative with respect to time of the receiver's replica of the transmitted waveform and the received waveform. The initial investigation involved calculating the phase information generated by this phase discriminator for a variety of code-phase and frequency offsets. It was found that there were two stable points in the baseband Spread Spectrum search grid, a grid where a cell consists of a certain code-phase and frequency offset. These stable points existed at no frequency offset, which means that the loops should track the input frequency, and a one or no code-phase offset, which means that the loops should acquire either code-phase. A simple model where the novel synchronisation loop's conditions are represented by a 'ball' resting on the baseband Spread Spectrum search grid as expressed in terms of the integrated phase output of the maximal likelihood phase discriminator was developed. In this model the 'ball' will roll around the surface until one of the two stable points is entered. This describes quite accurately the paths the novel synchronisation loop does in fact take through the baseband Spread Spectrum search grid. The first loop is based directly on the maximal likelihood phase detector. The differentiator is thus in the feedback path of the loop. This results in the loop being unstable and parameter sensitive. Moving the differentiator into the input path, as in the second loop, resulted in a more stable loop. This loop therefore offered a complete, simple synchronisation solution. The novel synchronisation loop with the differentiator in the input path was found to operate at signal-to- noise ratios of -2 dB. Improvement of this signal-to-noise ratio does not offer any advantages in a Spread Spectrum environment as the loop needs to work in a coherent system where the radio frequency carrier must be resolved before the receiver's pseudo-noise sequence can be synchronised. A radio frequency carrier cannot be easily resolved at signal-to-noise ratios lower than O dB. The loop was further adapted to operate in the data environment. Under conditions of data modulation the received waveform is randomly inverted by the data. This results in the loop being driven out of lock. The phase discriminator's slope, having locked on a certain polarity, cannot track an input of the opposite polarity. The loop was adapted by including detection circuitry that would monitor the state of the receiver with respect to the incoming data waveform and alter the polarity of the of the discriminator's slope where necessary. During the prototyping of the loop on the bench certain implementations were investigated. These included the signed edge detector, a wideband low noise implementation of a square wave differentiator, and the synchronous oscillator, a form of injection locked oscillator. The loop was shown to achieve synchronisation. The novel synchronisation loop with the differentiator in the input path is thus capable of synchronising two maximal-length sequences in both code-phase and frequency

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Design and Test of a Gate Driver with Variable Drive and Self-Test Capability Implemented in a Silicon Carbide CMOS Process

Discrete silicon carbide (SiC) power devices have long demonstrated abilities that outpace those of standard silicon (Si) parts. The improved physical characteristics allow for faster switching, lower on-resistance, and temperature performance. The capabilities unleashed by these devices allow for higher efficiency switch-mode converters as well as the advance of power electronics into new high-temperature regimes previously unimaginable with silicon devices. While SiC power devices have reached a relative level of maturity, recent work has pushed the temperature boundaries of control electronics further with silicon carbide integrated circuits. The primary requirement to ensure rapid switching of power MOSFETs was a gate drive buffer capable of taking a control signal and driving the MOSFET gate with high current required. In this work, the first integrated SiC CMOS gate driver was developed in a 1.2 μm SiC CMOS process to drive a SiC power MOSFET. The driver was designed for close integration inside a power module and exposure to high temperatures. The drive strength of the gate driver was controllable to allow for managing power MOSFET switching speed and potential drain voltage overshoot. Output transistor layouts were optimized using custom Python software in conjunction with existing design tool resources. A wafer-level test system was developed to identify yield issues in the gate driver output transistors. This method allowed for qualitative and quantitative evaluation of transistor leakage while the system was under probe. Wafer-level testing and results are presented. The gate driver was tested under high temperature operation up to 530 degrees celsius. An integrated module was built and tested to illustrate the capability of the gate driver to control a power MOSFET under load. The adjustable drive strength feature was successfully demonstrated

JUNO Conceptual Design Report

The Jiangmen Underground Neutrino Observatory (JUNO) is proposed to determine the neutrino mass hierarchy using an underground liquid scintillator detector. It is located 53 km away from both Yangjiang and Taishan Nuclear Power Plants in Guangdong, China. The experimental hall, spanning more than 50 meters, is under a granite mountain of over 700 m overburden. Within six years of running, the detection of reactor antineutrinos can resolve the neutrino mass hierarchy at a confidence level of 3-4$\sigma$, and determine neutrino oscillation parameters $\sin^2\theta_{12}$, $\Delta m^2_{21}$, and $|\Delta m^2_{ee}|$ to an accuracy of better than 1%. The JUNO detector can be also used to study terrestrial and extra-terrestrial neutrinos and new physics beyond the Standard Model. The central detector contains 20,000 tons liquid scintillator with an acrylic sphere of 35 m in diameter. $\sim$17,000 508-mm diameter PMTs with high quantum efficiency provide $\sim$75% optical coverage. The current choice of the liquid scintillator is: linear alkyl benzene (LAB) as the solvent, plus PPO as the scintillation fluor and a wavelength-shifter (Bis-MSB). The number of detected photoelectrons per MeV is larger than 1,100 and the energy resolution is expected to be 3% at 1 MeV. The calibration system is designed to deploy multiple sources to cover the entire energy range of reactor antineutrinos, and to achieve a full-volume position coverage inside the detector. The veto system is used for muon detection, muon induced background study and reduction. It consists of a Water Cherenkov detector and a Top Tracker system. The readout system, the detector control system and the offline system insure efficient and stable data acquisition and processing.Comment: 328 pages, 211 figure

Design-for-delay-testability techniques for high-speed digital circuits

The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud getting more and more important

Energy/power consumption model for an embedded processor board

This dissertation, whose research has been conducted at the Group of Electronic and Microelectronic Design (GDEM) within the framework of the project Power Consumption Control in Multimedia Terminals (PCCMUTE), focuses on the development of an energy estimation model for the battery-powered embedded processor board. The main objectives and contributions of the work are summarized as follows: A model is proposed to obtain the accurate energy estimation results based on the linear correlation between the performance monitoring counters (PMCs) and energy consumption. the uniqueness of the appropriate PMCs for each different system, the modeling methodology is improved to obtain stable accuracies with slight variations among multiple scenarios and to be repeatable in other systems. It includes two steps: the former, the PMC-filter, to identify the most proper set among the available PMCs of a system and the latter, the k-fold cross validation method, to avoid the bias during the model training stage. The methodology is implemented on a commercial embedded board running the 2.6.34 Linux kernel and the PAPI, a cross-platform interface to configure and access PMCs. The results show that the methodology is able to keep a good stability in different scenarios and provide robust estimation results with the average relative error being less than 5%. Este trabajo fin de máster, cuya investigación se ha desarrollado en el Grupo de Diseño Electrónico y Microelectrónico (GDEM) en el marco del proyecto PccMuTe, se centra en el desarrollo de un modelo de estimación de energía para un sistema empotrado alimentado por batería. Los objetivos principales y las contribuciones de esta tesis se resumen como sigue: Se propone un modelo para obtener estimaciones precisas del consumo de energía de un sistema empotrado. El modelo se basa en la correlación lineal entre los valores de los contadores de prestaciones y el consumo de energía. Considerando la particularidad de los contadores de prestaciones en cada sistema, la metodología de modelado se ha mejorado para obtener precisiones estables, con ligeras variaciones entre escenarios múltiples y para replicar los resultados en diferentes sistemas. La metodología incluye dos etapas: la primera, filtrado-PMC, que consiste en identificar el conjunto más apropiado de contadores de prestaciones de entre los disponibles en un sistema y la segunda, el método de validación cruzada de K iteraciones, cuyo fin es evitar los sesgos durante la fase de entrenamiento. La metodología se implementa en un sistema empotrado que ejecuta el kernel 2.6.34 de Linux y PAPI, un interfaz multiplataforma para configurar y acceder a los contadores. Los resultados muestran que esta metodología consigue una buena estabilidad en diferentes escenarios y proporciona unos resultados robustos de estimación con un error medio relativo inferior al 5%