165 research outputs found
Optimized Surface Code Communication in Superconducting Quantum Computers
Quantum computing (QC) is at the cusp of a revolution. Machines with 100
quantum bits (qubits) are anticipated to be operational by 2020
[googlemachine,gambetta2015building], and several-hundred-qubit machines are
around the corner. Machines of this scale have the capacity to demonstrate
quantum supremacy, the tipping point where QC is faster than the fastest
classical alternative for a particular problem. Because error correction
techniques will be central to QC and will be the most expensive component of
quantum computation, choosing the lowest-overhead error correction scheme is
critical to overall QC success. This paper evaluates two established quantum
error correction codes---planar and double-defect surface codes---using a set
of compilation, scheduling and network simulation tools. In considering
scalable methods for optimizing both codes, we do so in the context of a full
microarchitectural and compiler analysis. Contrary to previous predictions, we
find that the simpler planar codes are sometimes more favorable for
implementation on superconducting quantum computers, especially under
conditions of high communication congestion.Comment: 14 pages, 9 figures, The 50th Annual IEEE/ACM International Symposium
on Microarchitectur
Resource Optimized Quantum Architectures for Surface Code Implementations of Magic-State Distillation
Quantum computers capable of solving classically intractable problems are
under construction, and intermediate-scale devices are approaching completion.
Current efforts to design large-scale devices require allocating immense
resources to error correction, with the majority dedicated to the production of
high-fidelity ancillary states known as magic-states. Leading techniques focus
on dedicating a large, contiguous region of the processor as a single
"magic-state distillation factory" responsible for meeting the magic-state
demands of applications. In this work we design and analyze a set of optimized
factory architectural layouts that divide a single factory into spatially
distributed factories located throughout the processor. We find that
distributed factory architectures minimize the space-time volume overhead
imposed by distillation. Additionally, we find that the number of distributed
components in each optimal configuration is sensitive to application
characteristics and underlying physical device error rates. More specifically,
we find that the rate at which T-gates are demanded by an application has a
significant impact on the optimal distillation architecture. We develop an
optimization procedure that discovers the optimal number of factory
distillation rounds and number of output magic states per factory, as well as
an overall system architecture that interacts with the factories. This yields
between a 10x and 20x resource reduction compared to commonly accepted single
factory designs. Performance is analyzed across representative application
classes such as quantum simulation and quantum chemistry.Comment: 16 pages, 14 figure
2D Qubit Placement of Quantum Circuits using LONGPATH
In order to achieve speedup over conventional classical computing for finding
solution of computationally hard problems, quantum computing was introduced.
Quantum algorithms can be simulated in a pseudo quantum environment, but
implementation involves realization of quantum circuits through physical
synthesis of quantum gates. This requires decomposition of complex quantum
gates into a cascade of simple one qubit and two qubit gates. The
methodological framework for physical synthesis imposes a constraint regarding
placement of operands (qubits) and operators. If physical qubits can be placed
on a grid, where each node of the grid represents a qubit then quantum gates
can only be operated on adjacent qubits, otherwise SWAP gates must be inserted
to convert non-Linear Nearest Neighbor architecture to Linear Nearest Neighbor
architecture. Insertion of SWAP gates should be made optimal to reduce
cumulative cost of physical implementation. A schedule layout generation is
required for placement and routing apriori to actual implementation. In this
paper, two algorithms are proposed to optimize the number of SWAP gates in any
arbitrary quantum circuit. The first algorithm is intended to start with
generation of an interaction graph followed by finding the longest path
starting from the node with maximum degree. The second algorithm optimizes the
number of SWAP gates between any pair of non-neighbouring qubits. Our proposed
approach has a significant reduction in number of SWAP gates in 1D and 2D NTC
architecture.Comment: Advanced Computing and Systems for Security, SpringerLink, Volume 1
On the Effect of Quantum Interaction Distance on Quantum Addition Circuits
We investigate the theoretical limits of the effect of the quantum
interaction distance on the speed of exact quantum addition circuits. For this
study, we exploit graph embedding for quantum circuit analysis. We study a
logical mapping of qubits and gates of any -depth quantum adder
circuit for two -qubit registers onto a practical architecture, which limits
interaction distance to the nearest neighbors only and supports only one- and
two-qubit logical gates. Unfortunately, on the chosen -dimensional practical
architecture, we prove that the depth lower bound of any exact quantum addition
circuits is no longer , but . This
result, the first application of graph embedding to quantum circuits and
devices, provides a new tool for compiler development, emphasizes the impact of
quantum computer architecture on performance, and acts as a cautionary note
when evaluating the time performance of quantum algorithms.Comment: accepted for ACM Journal on Emerging Technologies in Computing
System
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