A Review on Design and Development of Pipelined Quaternary Adder for Fast Addition

Design of the binary logic circuits is limited by the requirement of the interconnections. A possible solution could be arrived at by using a larger set of signals over the same chip area. Multiple-valued logic (MVL) designs are gaining importance from that perspective. This paper presents the design of a multiple-valued half adder and full adder circuits. In Quaternary adders the binary value is first converted into the Quaternary value and then the addition operation is performed with less number of gates and minimum depth of net. Sum and carry are processed in two separate blocks, controlled by code generator unit. Simple pass transistors are used for implementation. Area of the designed circuits is less than the corresponding binary circuits and quaternary adders because number of transistors used are less. We can implement this paper by using pipelining which help us to reduce the delay of operation and also help us to improve the throughput of the system, the designing of the paper is done by using VHDL. DOI: 10.17762/ijritcc2321-8169.15034

ハードウェアリソースの高稼働率化に基づく細粒度多値リコンフィギャラブルVLSIアーキテクチャ

Tohoku University亀山充隆課

Design and Implementation 4-Bit Quaternary MVL Arithmetic and Logic Unit

In the recent years, there were major importance to Multiple Valued Logic (MVL), where the most common reasons for considering the implementation of MVL circuits better then binary valued circuits are that reducing wiring congestion as compared to binary circuits, using a single conductor to transmit three or more discrete voltage or current values allows for greater information content per wire and the circuit cost models would be more economical. Therefore, in this paper the MVL concepts have been used to design 4-bit quaternary MVL Arithmetic and Logic Unit, which is considered a basic unit of a MVL microprocessor. It is the "heart" of a microprocessor and we could say that everything else in the microprocessor is there to support the ALU. The proposed Arithmetic and Logic Unit will do the operations as Addition, Subtraction, Maximum, Minimum and Invert. Simulation Program with Integrated Circuit Emphasis (SPICE) tool in Cadence simulator used in simulation the proposed Arithmetic and Logic Unit. The simulation results tells that the design is more efficient compared with the binary ALU and the circuit will be less area and less number of transistors

Ternary and quaternary logic to binary bit conversion CMOS integrated circuit design using multiple input floating gate MOSFETs

Multiple-input floating gate MOSFETs and floating gate potential diagrams have been used for conversion of ternary-valued input and quaternary-valued input into corresponding binary-valued output in CMOS integrated circuit design environment. The method is demonstrated through the design of a circuit for conversion of ternary inputs 00 to -1-1 (decimal 0 to -4) and 00 to 11 (decimal 0 to +4) into the corresponding binary bits and for conversion of quaternary inputs (decimal 0 to 3) into the corresponding binary bits (binary 00 to 11) in a standard 1.5 mm digital CMOS technology. The physical design of the circuits is simulated and tested with SPICE using MOSIS BSIM3 model parameters. The conversion method is simple and compatible with the present CMOS process. The circuits could be embedded in digital CMOS VLSI design architectures. The conversion circuit for ternary inputs into corresponding binary outputs has maximum propagation delay of 8 ns with 0.1 pF simulated capacitive load. The physical layout design occupies an area of 432´908 mm2. The conversion circuit for quaternary inputs to corresponding binary outputs has maximum propagation delay of 6 ns with 0.1 pF simulated capacitive load. The physical layout design occupies an area of 130´175 mm2. The conversion circuit achieved significant improvement in the number of devices. A reduction of more than 75% in transistor count was obtained over the previous designs. Measurements of the fabricated devices for the conversion of quaternary input into binary output agree with simulated values

The implementation and applications of multiple-valued logic

Multiple-Valued Logic (MVL) takes two major forms. Multiple-valued circuits can implement the logic directly by using multiple-valued signals, or the logic can be implemented indirectly with binary circuits, by using more than one binary signal to represent a single multiple-valued signal. Techniques such as carry-save addition can be viewed as indirectly implemented MVL. Both direct and indirect techniques have been shown in the past to provide advantages over conventional arithmetic and logic techniques in algorithms required widely in computing for applications such as image and signal processing. It is possible to implement basic MVL building blocks at the transistor level. However, these circuits are difficult to design due to their non binary nature. In the design stage they are more like analogue circuits than binary circuits. Current integrated circuit technologies are biased towards binary circuitry. However, in spite of this, there is potential for power and area savings from MVL circuits, especially in technologies such as BiCMOS. This thesis shows that the use of voltage mode MVL will, in general not provide bandwidth increases on circuit buses because the buses become slower as the number of signal levels increases. Current mode MVL circuits however do have potential to reduce power and area requirements of arithmetic circuitry. The design of transistor level circuits is investigated in terms of a modern production technology. A novel methodology for the design of current mode MVL circuits is developed. The methodology is based upon the novel concept of the use of non-linear current encoding of signals, providing the opportunity for the efficient design of many previously unimplemented circuits in current mode MVL. This methodology is used to design a useful set of basic MVL building blocks, and fabrication results are reported. The creation of libraries of MVL circuits is also discussed. The CORDIC algorithm for two dimensional vector rotation is examined in detail as an example for indirect MVL implementation. The algorithm is extended to a set of three dimensional vector rotators using conventional arithmetic, redundant radix four arithmetic, and Taylor's series expansions. These algorithms can be used for two dimensional vector rotations in which no scale factor corrections are needed. The new algorithms are compared in terms of basic VLSI criteria against previously reported algorithms. A pipelined version of the redundant arithmetic algorithm is floorplanned and partially laid out to give indications of wiring overheads, and layout densities. An indirectly implemented MVL algorithm such as the CORDIC algorithm described in this thesis would clearly benefit from direct implementation in MVL

REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS

New radar applications need to perform complex algorithms and process a large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low-power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression algorithms for real-time transceiver optimization is presented, and is based on a System-on-Chip architecture for reconfigurable hardware devices. This study also evaluates the performance of dedicated coprocessors as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion, which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through high-performance buses, to perform floating-point operations, control the processing blocks, and communicate with an external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band testbed together with a low-cost channel emulator for different types of waveforms

A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM

In this article, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in the OFDM based IEEE 802.11a Wireless LAN (WLAN) baseband processor. The 64-point FFT is realized by decomposing it into a 2-D structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use any 2-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64-point FFT/IFFT processor has been fabricated and tested successfully using our in-house 0.25 ?m BiCMOS technology. The core area of this chip is 6.8 mm2. The average dynamic power consumption is 41 mW @ 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-to-parallel (i. e., when all input data are available in parallel and all output data are generated in parallel) 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption

Arithmetic logic UNIT (ALU) design using reconfigurable CMOS logic

Using the reconfigurable logic of multi-input floating gate MOSFETs, a 4-bit ALU has been designed for 3V operation. The ALU can perform four arithmetic and four logical operations. Multi- input floating gate (MIFG) transistors have been promising in realizing increased functionality on a chip. A multi- input floating gate MOS transistor accepts multiple inputs signals, calculates the weighted sum of all input signals and then controls the ON and OFF states of the transistor. This enhances the transistor function to more than just switching. This changes the way a logic function can be realized. Implementing a design using multi-input floating gate MOSFETs brings about reduction in transis tor count and number of interconnections. The advantage of bringing down the number of devices is that a design becomes area efficient and power consumption reduces. There are several applications that stress on smaller chip area and reduced power. Multi- input floating gate devices have their use in memories, analog and digital circuits. In the present work we have shown successful implementation of multi- input floating gate MOSFETs in ALU design. A comparison has been made between adders using different design methods w.r.t transistor count. It is seen that our design, implemented using multi-input floating gate MOSFETs, uses the least number of transistors when compared to other designs. The design was fabricated using double polysilicon standard CMOS process by MOSIS in 1.5mm technology. The experimental waveforms and delay measurements have also been presented