28,067 research outputs found
Implications of Electronics Constraints for Solid-State Quantum Error Correction and Quantum Circuit Failure Probability
In this paper we present the impact of classical electronics constraints on a
solid-state quantum dot logical qubit architecture. Constraints due to routing
density, bandwidth allocation, signal timing, and thermally aware placement of
classical supporting electronics significantly affect the quantum error
correction circuit's error rate. We analyze one level of a quantum error
correction circuit using nine data qubits in a Bacon-Shor code configured as a
quantum memory. A hypothetical silicon double quantum dot quantum bit (qubit)
is used as the fundamental element. A pessimistic estimate of the error
probability of the quantum circuit is calculated using the total number of
gates and idle time using a provably optimal schedule for the circuit
operations obtained with an integer program methodology. The micro-architecture
analysis provides insight about the different ways the electronics impact the
circuit performance (e.g., extra idle time in the schedule), which can
significantly limit the ultimate performance of any quantum circuit and
therefore is a critical foundation for any future larger scale architecture
analysis.Comment: 10 pages, 7 figures, 3 table
Circuit Transformations for Quantum Architectures
Quantum computer architectures impose restrictions on qubit interactions. We propose efficient circuit transformations that modify a given quantum circuit to fit an architecture, allowing for any initial and final mapping of circuit qubits to architecture qubits. To achieve this, we first consider the qubit movement subproblem and use the ROUTING VIA MATCHINGS framework to prove tighter bounds on parallel routing. In practice, we only need to perform partial permutations, so we generalize ROUTING VIA MATCHINGS to that setting. We give new routing procedures for common architecture graphs and for the generalized hierarchical product of graphs, which produces subgraphs of the Cartesian product. Secondly, for serial routing, we consider the TOKEN SWAPPING framework and extend a 4-approximation algorithm for general graphs to support partial permutations. We apply these routing procedures to give several circuit transformations, using various heuristic qubit placement subroutines. We implement these transformations in software and compare their performance for large quantum circuits on grid and modular architectures, identifying strategies that work well in practice
A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs
Crosstalk computing, involving engineered interference between nanoscale
metal lines, offers a fresh perspective to scaling through co-existence with
CMOS. Through capacitive manipulations and innovative circuit style, not only
primitive gates can be implemented, but custom logic cells such as an Adder,
Subtractor can be implemented with huge gains. Our simulations show over 5x
density and 2x power benefits over CMOS custom designs at 16nm [1]. This paper
introduces the Crosstalk circuit style and a key method for large-scale circuit
synthesis utilizing existing EDA tool flow. We propose to manipulate the CMOS
synthesis flow by adding two extra steps: conversion of the gate-level netlist
to Crosstalk implementation friendly netlist through logic simplification and
Crosstalk gate mapping, and the inclusion of custom cell libraries for
automated placement and layout. Our logic simplification approach first
converts Cadence generated structured netlist to Boolean expressions and then
uses the majority synthesis tool to obtain majority functions, which is further
used to simplify functions for Crosstalk friendly implementations. We compare
our approach of logic simplification to that of CMOS and majority logic-based
approaches. Crosstalk circuits share some similarities to majority synthesis
that are typically applied to Quantum Cellular Automata technology. However,
our investigation shows that by closely following Crosstalk's core circuit
styles, most benefits can be achieved. In the best case, our approach shows 36%
density improvements over majority synthesis for MCNC benchmark
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