Equalization of Third-Order Intermodulation Products in Wideband Direct Conversion Receivers

This paper reports a SAW-less direct-conversion receiver which utilizes a mixed-signal feedforward path to regenerate and adaptively cancel IM3 products, thus accomplishing system-level linearization. The receiver system performance is dominated by a custom integrated RF front end implemented in 130-nm CMOS and achieves an uncorrected out-of-band IIP3 of -7.1 dBm under the worst-case UMTS FDD Region 1 blocking specifications. Under IM3 equalization, the receiver achieves an effective IIP3 of +5.3 dBm and meets the UMTS BER sensitivity requirement with 3.7 dB of margin

Efficient and Interference-Resilient Wireless Connectivity for IoT Applications

With the coming of age of the Internet of Things (IoT), demand on ultra-low power (ULP) and low-cost radios will continue to boost tremendously. The Bluetooth-Low-energy (BLE) standard provides a low power solution to connect IoT nodes with mobile devices, however, the power of maintaining a connection with a reasonable latency remains the limiting factor in defining the lifetime of event-driven BLE devices. BLE radio power consumption is in the milliwatt range and can be duty cycled for average powers around 30μW, but at the expense of long latency. Furthermore, wireless transceivers traditionally perform local oscillator (LO) calibration using an external crystal oscillator (XTAL) that adds significant size and cost to a system. Removing the XTAL enables a true single-chip radio, but an alternate means for calibrating the LO is required. Innovations in both the system architecture and circuits implementation are essential for the design of truly ubiquitous receivers for IoT applications. This research presents two porotypes as back-channel BLE receivers, which have lower power consumption while still being robust in the presents of interference and able to receive back-channel message from BLE compliant transmitters. In addition, the first crystal-less transmitter with symmetric over-the-air clock recovery compliant with the BLE standard using a GFSK-Modulated BLE Packet is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162942/1/abdulalg_1.pd

High-speed Time-interleaved Digital-to-Analog Converter (TI-DAC) for Self-Interference Cancellation Applications

Nowadays, the need for higher data-rate is constantly growing to enhance the quality of the daily communication services. The full-duplex (FD) communication is exemplary method doubling the data-rate compared to half-duplex one. However, part of the strong output signal of the transmitter interferes to the receiver-side because they share the same antenna with limited attenuation and, as a result, the receiver’s performance is corrupted. Hence, it is critical to remove the leakage signal from the receiver’s path by designing another block called self-interference cancellation (SIC). The main goal of this dissertation is to develop the SIC block embedded in the current-mode FD receivers. To this end, the regenerated cancellation current signal is fed to the inputs of the base-band filter and after the mixer of a (direct-conversion) current-mode FD receiver. Since the pattern of the transmitter (the digital signal generated by DSP) is known, a high-speed digital-to-Analog converter (DAC) with medium-resolution can perfectly suppress main part of the leakage on the receiver path. A capacitive DAC (CDAC) is chosen among the available solutions because it is compatible with advanced CMOS technology for high-speed application and the medium-resolution designs. Although the main application of the design is to perform the cancellation, it can also be employed as a stand-alone DAC in the Analog (I/Q) transmitter. The SIC circuitry includes a trans-impedance amplifier (TIA), two DACs, high-speed digital circuits, and built-in-self-test section (BIST). According to the available specification for full-duplex communication system, the resolution and working frequency of the CDAC are calculated (designed) equal to 10-bit (3 binary+ 2 binary + 5 thermometric) and 1GHz, respectively. In order to relax the design of the TIA (settling time of the DAC), the CDAC implements using 2-way time-interleaved (TI) manner (the effective SIC frequency equals 2GHz) without using any calibration technique. The CDAC is also developed with the split-capacitor technique to lower the negative effects of the conventional binary-weighted DAC. By adding one extra capacitor on the left-side of the split-capacitor, LSB-side, the value of the split-capacitor can be chosen as an integer value of the unit capacitor. As a result, it largely enhances the linearity of the CADC and cancellation performance. If the block works as a stand-alone DAC with non-TI mode, the digital input code representing a Sinus waveform with an amplitude 1dB less than full-scale and output frequency around 10.74MHz, chosen by coherent sampling rule, then the ENOB, SINAD, SFDR, and output signal are 9.4-bit, 58.2 dB, 68.4dBc, and -9dBV. The simulated value of the |DNL| (static linearity) is also less than 0.7. The similar simulation was done in the SIC mode while the capacitive-array woks in the TI mode and cancellation current is set to the full-scale. Hence, the amount of cancelling the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. equals 51.3dB, 15.1 dB, 24dBc, 66.4 dB. The designed SIC cannot work as a closed-loop design. The layout was optimally drawn in order to minimize non-linearity, the power-consumption of the decoders, and reduce the complexity of the DAC. By distributing the thermometric cells across the array and using symmetrical switching scheme, the DAC is less subjected to the linear and gradient effect of the oxide. Based on the post-layout simulation results, the deviation of the design after drawing the layout is studied. To compare the results of the schematic and post-layout designs, the exact conditions of simulation above (schematic simulations) are used. When the block works as a stand-alone CDAC, the ENOB, SINAD, SFDR are 8.5-bit, 52.6 dB, 61.3 dBc. The simulated value of the |DNL| (static linearity) is also limited to 1.3. Likewise, the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. are equal to 44dB, 11.7 dB, 19 dBc, 55.7 dB

System-Level Design of All-Digital LTE / LTE-A Transmitter Hardware

This thesis presents a detailed system-level analysis of an all-digital transmitter hardware based on the Direct-Digital RF-Modulator (DDRM). The purpose of the presented analysis is to evaluate whether this particular transmitter architecture is suitable to be used in LTE / LTE-A mobile phones. The DDRM architecture is based on the Radio Frequency Digital-to-Analog Converter (RF-DAC), whose system-level characteristics are investigated in this work through mathematical analysis and MATLAB simulations. In particular, a new analytical model for the timing error in the distributed upconversion is developed and verified. Moreover, this thesis reviews the LTE and LTE-A standards, and describes how a baseband environment for signal generation/demodulation can be implemented in MATLAB. The presented system enables much more flexibility with respect to current commercial softwares like Agilent Signal Studio. Simulation results show that the most challenging specification to meet is the out-of-band noise floor, because of the stringent linearity and timing requirements posed on the RF-DAC. This suggests that new means of reducing the out-of-band noise in all-digital transmitters should be researched, in order not to make their design more complicated than for their analog counterpart

Computational Complexity of Signal Processing Functions in Software Radio

The increased usage of mobile communication devices has imposed a challenge of achieving efficient communication with minimum power consumption. Moreover, with the advent of software defined radios (SDR), it is highly possible that signal processing functions would be implemented in software in future mobile devices. Hence, the power consumption of these future devices will be directly related to the power consumed by the processor that executes SDR software. This thesis aims at analyzing the computational complexity of different modulation schemes and signal processing communication functions of IEEE WiFi standard. This analysis provides good insight on how the computational load varies at different data rates for different modulation schemes. For this purpose, we have analyzed computational complexity of various modulation schemes and other communication functions using widely known software radio platform i.e. USRP hardware and GNU Radio open source software platform, Matlab and OProfile (open source Linux profiling tool). After performing an extensive analysis, we are able to determine how different modulation schemes and communication functions perform computationally on a given platform. This analysis would help to achieve effective communication along with the efficient use of power in SDR based system

Computational Complexity of Signal Processing Functions in Software Radio

The increased usage of mobile communication devices has imposed a challenge of achieving efficient communication with minimum power consumption. Moreover, with the advent of software defined radios (SDR), it is highly possible that signal processing functions would be implemented in software in future mobile devices. Hence, the power consumption of these future devices will be directly related to the power consumed by the processor that executes SDR software. This thesis aims at analyzing the computational complexity of different modulation schemes and signal processing communication functions of IEEE WiFi standard. This analysis provides good insight on how the computational load varies at different data rates for different modulation schemes. For this purpose, we have analyzed computational complexity of various modulation schemes and other communication functions using widely known software radio platform i.e. USRP hardware and GNU Radio open source software platform, Matlab and OProfile (open source Linux profiling tool). After performing an extensive analysis, we are able to determine how different modulation schemes and communication functions perform computationally on a given platform. This analysis would help to achieve effective communication along with the efficient use of power in SDR based system

Computational Complexity of Signal Processing Functions in Software Radio

The increased usage of mobile communication devices has imposed a challenge of achieving efficient communication with minimum power consumption. Moreover, with the advent of software defined radios (SDR), it is highly possible that signal processing functions would be implemented in software in future mobile devices. Hence, the power consumption of these future devices will be directly related to the power consumed by the processor that executes SDR software. This thesis aims at analyzing the computational complexity of different modulation schemes and signal processing communication functions of IEEE WiFi standard. This analysis provides good insight on how the computational load varies at different data rates for different modulation schemes. For this purpose, we have analyzed computational complexity of various modulation schemes and other communication functions using widely known software radio platform i.e. USRP hardware and GNU Radio open source software platform, Matlab and OProfile (open source Linux profiling tool). After performing an extensive analysis, we are able to determine how different modulation schemes and communication functions perform computationally on a given platform. This analysis would help to achieve effective communication along with the efficient use of power in SDR based system