Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance

CMOS Data Converters for Closed-Loop mmWave Transmitters

With the increased amount of data consumed in mobile communication systems, new solutions for the infrastructure are needed. Massive multiple input multiple output (MIMO) is seen as a key enabler for providing this increased capacity. With the use of a large number of transmitters, the cost of each transmitter must be low. Closed-loop transmitters, featuring high-speed data converters is a promising option for achieving this reduced unit cost.In this thesis, both digital-to-analog (D/A) and analog-to-digital (A/D) converters suitable for wideband operation in millimeter wave (mmWave) massive MIMO transmitters are demonstrated. A 2 76 bit radio frequency digital-to-analog converter (RF-DAC)-based in-phase quadrature (IQ) modulator is demonstrated as a compact building block, that to a large extent realizes the transmit path in a closed-loop mmWave transmitter. The evaluation of an successive-approximation register (SAR) analog-to-digital converter (ADC) is also presented in this thesis. Methods for connecting simulated and measured performance has been studied in order to achieve a better understanding about the alternating comparator topology.These contributions show great potential for enabling closed-loop mmWave transmitters for massive MIMO transmitter realizations

A digital polar transmitter for multi-band OFDM Ultra-WideBand

Linear power amplifiers used to implement the Ultra-Wideband standard must be backed off from optimum power efficiency to meet the standard specifications and the power efficiency suffers. The problem of low efficiency can be mitigated by polar modulation. Digital polar architectures have been employed on numerous wireless standards like GSM, EDGE, and WLAN, where the fractional bandwidths achieved are only about 1%, and the power levels achieved are often in the vicinity of 20 dBm. Can the architecture be employed on wireless standards with low-power and high fractional bandwidth requirements and yet achieve good power efficiency? To answer these question, this thesis studies the application of a digital polar transmitter architecture with parallel amplifier stages for UWB. The concept of the digital transmitter is motivated and inspired by three factors. First, unrelenting advances in the CMOS technology in deep-submicron process and the prevalence of low-cost Digital Signal processing have resulted in the realization of higher level of integration using digitally intensive approaches. Furthermore, the architecture is an evolution of polar modulation, which is known for high power efficiency in other wireless applications. Finally, the architecture is operated as a digital-to-analog converter which circumvents the use of converters in conventional transmitters. Modeling and simulation of the system architecture is performed on the Agilent Advanced Design System Ptolemy simulation platform. First, by studying the envelope signal, we found that envelope clipping results in a reduction in the peak-to-average power ratio which in turn improves the error vector magnitude performance (figure of merit for the study). In addition, we have demonstrated that a resolution of three bits suffices for the digital polar transmitter when envelope clipping is performed. Next, this thesis covers a theoretical derivation for the estimate of the error vector magnitude based on the resolution, quantization and phase noise errors. An analysis on the process variations - which result in gain and delay mismatches - for a digital transmitter architecture with four bits ensues. The above studies allow RF designers to estimate the number of bits required and the amount of distortion that can be tolerated in the system. Next, a study on the circuit implementation was conducted. A DPA that comprises 7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7 cascode transistors (individually connected in series with the bottom amplifiers) digitally controlled by a 3-bit digitized envelope signal to reconstruct the UWB signal at the output. Through the use of NFET models from the IBM 130-nm technology, our simulation reveals that our DPA is able to achieve an EVM of - 22 dB. The DPA simulations have been performed at 3.432 GHz centre frequency with a channel bandwidth of 528 MHz, which translates to a fractional bandwidth of 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while delivering -1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power. In addition, we performed a yield analysis on the digital polar amplifier, based on unit-weighted and binary-weighted architecture, when gain variations are introduced in all the individual stages. The dynamic element matching method is also introduced for the unit-weighted digital polar transmitter. Monte Carlo simulations reveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with a standard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%, while the yields of the unit-weighted architectures are in the neighbourhood of 95%. Moreover, the dynamic element matching technique demonstrates an improvement in the yield by approximately 3%. Finally, a hardware implementation for this architecture based on software-defined arbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polar transmitter under ideal combining conditions fulfill the European Computer Manufacturers Association requirements. The proposed experimental setup, believed to be the first ever attempted, confirm the feasibility of a digital polar transmitter architecture for Ultra-Wideband. In addition, we propose a number of power combining techniques suitable for the hardware implementation. Spatial power combining, in particular, shows a high potential for the digital polar transmitter architecture. The above studies demonstrate the feasibility of the digital polar architecture with good power efficiency for a wideband wireless standard with low-power and high fractional bandwidth requirements

Communications techniques and equipment: A compilation

This Compilation is devoted to equipment and techniques in the field of communications. It contains three sections. One section is on telemetry, including articles on radar and antennas. The second section describes techniques and equipment for coding and handling data. The third and final section includes descriptions of amplifiers, receivers, and other communications subsystems

Evaluation of Sigma-Delta-over-Fiber for High-Speed Wireless Applications

Future mobile communication networks aim to increase the communication speed,\ua0provide better reliability and improve the coverage. It needs to achieve all of these enhancements, while the number of users are increasing drastically. As a result, new base-station (BS) architectures where the signal processing is centralized and wireless access is provided through multiple, carefully coordinated remote radio heads are needed. Sigma-delta-over-fiber (SDoF) is a communication technique that can address both requirements and enable very low-complexity, phase coherent remote radio transmission, while transmitting wide-band communication signals with high quality. This thesis investigates the potential and limitations of SDoF communication links as an enabler for future mobile networks.In the first part of the thesis, an ultra-high-speed SDoF link is realized by using state-of-the-art vertical-cavity surface-emitting-lasers (VCSEL). The effects of VCSEL characteristics on such links in terms of signal quality, energy efficiency and potential lifespan is investigated. Furthermore, the potential and limitations of UHS-SDoF are evaluated with signals having various parameters. The results show that, low-cost, reliable, energy efficient, high signal quality SDoF links can be formed by using emerging VCSEL technology. Therefore, ultra-high-speed SDoF is a very promising technique for beyond 10~GHz communication systems.In the second part of the thesis, a multiple-input-multiple-output (MIMO) communication testbed with physically separated antenna elements, distributed-MIMO, is formed by multiple SDoF links. It is shown that the digital up-conversion, performed with a shared local-oscillator/clock at the central unit, provides excellent phase coherency between the physically distributed antenna elements. The proposed testbed demonstrates the advantages of SDoF for realizing distributed MIMO systems and is a powerful tool to perform various communication experiments in real environments.In general, SDoF is a solution for the downlink of a communication system, i.e. from central unit to remote radio head, however, the low complexity and low cost requirement of the remote radio heads makes it difficult to realize the uplinks of such systems. The third part of this thesis proposes an all-digital solution for realizing complementary uplinks for SDoF systems. The proposed structure is extensively investigated through simulations and measurements and the results demonstrate that it is possible realize all-digital, duplex, optical communication links between central units and remote radio heads.In summary, the results in this thesis demonstrate the potential of SDoF for wideband, distributed MIMO communication systems and proposes a new architecture for all-digital duplex communication links. Overall, the thesis shows that SDoF technique is powerful technique for emerging and future mobile communication networks, since it enables a centralized structure with low complexity remote radio heads and provides high signal quality

Multiband Analog-to-Digital Conversion

The current trend in the world of digital communications is the design of versatile devices that may operate using several different communication standards in order to increase the number of locations for which a particular device may be used. The signal is quantized early on in the reciever path by Analog-to-Digital Converters (ADCs), which allows the rest of the signal processing to be done by low complexity, low power digital circuits. For this reason, it is advantageous to create an architecture that can quantize different bandwidths at different frequencies to suit several different communication protocols. This thesis outlines the design of an architecture that uses multiple ADCs in parallel to quantize several different bandwidths of a wideband signal. A multirate filter bank is then applied to approximate perfect reconstruction of the wideband signal from its subband parts. This highly flexible architecture is able to quantize signals of varying bandwidths at a wide range of frequencies by using identical hardware in every channel, which also makes for a simple design. A prototype for the quantizer used in each channel, a frequency-selective fourth-order sigma-delta (CA ) ADC, was designed and fabricated in a 0.5 pm CMOS process. This device uses a switched-capacitor technique to implement the frequency selection in the front-end of the CA ADC in each channel. Running at a 5MHz sample rate, the device can select any of the first sixteen 156.25kHz wide bands for conversion. Testing results for this fabricated part are also presented

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Performance issues with photonic beamformers

A photonic beamformer is presented, having smooth behavior. Third-order nonlinearities, resulting from its optoelectronic components, are investigated, with emphasis on their impact on the contrast of imaging radars. This contrast is shown to be severely limited by the induced RF nonlinearities. Limitations on the allowable modulation index are studied for linearly-chirped pulses returned from clutter

Force feedback linearization for higher-order electromechanical sigma-delta modulators.

Abstract A higher-order electromechanical sigma–delta modulator can greatly improve the signal-to-noise ratio compared with a second-order loop that only uses the sensing element as a loop filter. However, the electrostatic force feedback on the proof mass is inherently nonlinear, which will produce harmonics in the output spectrum and limits the total signal-to-noise and distortion ratio. High performance inertial sensors, which use sigma–delta modulators as a closed-loop control system, have strict requirements on the output signal distortion. In this paper, nonlinear effects from the force feedback and pick-off circuits are analysed and a strategy for force feedback linearization is put forward which can considerably improve the signal-to-noise and distortion ratio. A PCB prototype of a fifth-order electromechanical modulator with a bulk micromachined accelerometer was used to demonstrate the concept