203 research outputs found

    Quantization effects in the polyphase N-path IIR structure

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    Polyphase IIR structures have recently proven themselves very attractive for very high performance filters that can be designed using very few coefficients. This, combined with their low sensitivity to coefficient quantization in comparison to standard FIR and IIR structures, makes them very applicable for very fast filtering when implemented in fixed-point arithmetic. However, although the mathematical description is very simple, there exist a number of ways to implement such filters. In this paper, we take four of these different implementation structures, analyze the rounding noise originating from the limited arithmetic wordlength of the mathematical operators, and check the internal data growth within the structure. These analyses need to be done to ensure that the performance of the implementation matches the performance of the theoretical design. The theoretical approach that we present has been proven by the results of the fixed-point simulation done in Simulink and verified by an equivalent bit-true implementation in VHDL

    One- and two-level filter-bank convolvers

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    In a recent paper, it was shown in detail that in the case of orthonormal and biorthogonal filter banks we can convolve two signals by directly convolving the subband signals and combining the results. In this paper, we further generalize the result. We also derive the statistical coding gain for the generalized subband convolver. As an application, we derive a novel low sensitivity structure for FIR filters from the convolution theorem. We define and derive a deterministic coding gain of the subband convolver over direct convolution for a fixed wordlength implementation. This gain serves as a figure of merit for the low sensitivity structure. Several numerical examples are included to demonstrate the usefulness of these ideas. By using the generalized polyphase representation, we show that the subband convolvers, linear periodically time varying systems, and digital block filtering can be viewed in a unified manner. Furthermore, the scheme called IFIR filtering is shown to be a special case of the convolver

    Design, analysis and evaluation of sigma-delta based beamformers for medical ultrasound imaging applications

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    The inherent analogue nature of medical ultrasound signals in conjunction with the abundant merits provided by digital image acquisition, together with the increasing use of relatively simple front-end circuitries, have created considerable demand for single-bit beamformers in digital ultrasound imaging systems. Furthermore, the increasing need to design lightweight ultrasound systems with low power consumption and low noise, provide ample justification for development and innovation in the use of single-bit beamformers in ultrasound imaging systems. The overall aim of this research program is to investigate, establish, develop and confirm through a combination of theoretical analysis and detailed simulations, that utilize raw phantom data sets, suitable techniques for the design of simple-to-implement hardware efficient digital ultrasound beamformers to address the requirements for 3D scanners with large channel counts, as well as portable and lightweight ultrasound scanners for point-of-care applications and intravascular imaging systems. In addition, the stability boundaries of higher-order High-Pass (HP) and Band-Pass (BP) Σ−Δ modulators for single- and dual- sinusoidal inputs are determined using quasi-linear modeling together with the describing-function method, to more accurately model the modulator quantizer. The theoretical results are shown to be in good agreement with the simulation results for a variety of input amplitudes, bandwidths, and modulator orders. The proposed mathematical models of the quantizer will immensely help speed up the design of higher order HP and BP Σ−Δ modulators to be applicable for digital ultrasound beamformers. Finally, a user friendly design and performance evaluation tool for LP, BP and HP modulators is developed. This toolbox, which uses various design methodologies and covers an assortment of modulators topologies, is intended to accelerate the design process and evaluation of modulators. This design tool is further developed to enable the design, analysis and evaluation of beamformer structures including the noise analyses of the final B-scan images. Thus, this tool will allow researchers and practitioners to design and verify different reconstruction filters and analyze the results directly on the B-scan ultrasound images thereby saving considerable time and effort

    Two-Path All-pass Based Half-Band Infinite Impulse Response Decimation Filters and the Effects of Their Non-Linear Phase Response on ECG Signal Acquisition

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    This paper is based on the novel use of a very high fidelity decimation filter chain for Electrocardiogram (ECG) signal acquisition and data conversion. The multiplier-free and multi-stage structure of the proposed filters lower the power dissipation while minimizing the circuit area which are crucial design constraints to the wireless noninvasive wearable health monitoring products due to the scarce operational resources in their electronic implementation. The decimation ratio of the presented filter is 128, working in tandem with a 1-bit 3rd order Sigma Delta (ΣΔ) modulator which achieves 0.04 dB passband ripples and -74 dB stopband attenuation. The work reported here investigates the non-linear phase effects of the proposed decimation filters on the ECG signal by carrying out a comparative study after phase correction. It concludes that the enhanced phase linearity is not crucial for ECG acquisition and data conversion applications since the signal distortion of the acquired signal, due to phase non-linearity, is insignificant for both original and phase compensated filters. To the best of the authors’ knowledge, being free of signal distortion is essential as this might lead to misdiagnosis as stated in the state of the art. This article demonstrates that with their minimal power consumption and minimal signal distortion features, the proposed decimation filters can effectively be employed in biosignal data processing units

    Design and Implementation of Complexity Reduced Digital Signal Processors for Low Power Biomedical Applications

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    Wearable health monitoring systems can provide remote care with supervised, inde-pendent living which are capable of signal sensing, acquisition, local processing and transmission. A generic biopotential signal (such as Electrocardiogram (ECG), and Electroencephalogram (EEG)) processing platform consists of four main functional components. The signals acquired by the electrodes are amplified and preconditioned by the (1) Analog-Front-End (AFE) which are then digitized via the (2) Analog-to-Digital Converter (ADC) for further processing. The local digital signal processing is usually handled by a custom designed (3) Digital Signal Processor (DSP) which is responsible for either anyone or combination of signal processing algorithms such as noise detection, noise/artefact removal, feature extraction, classification and compres-sion. The digitally processed data is then transmitted via the (4) transmitter which is renown as the most power hungry block in the complete platform. All the afore-mentioned components of the wearable systems are required to be designed and fitted into an integrated system where the area and the power requirements are stringent. Therefore, hardware complexity and power dissipation of each functional component are crucial aspects while designing and implementing a wearable monitoring platform. The work undertaken focuses on reducing the hardware complexity of a biosignal DSP and presents low hardware complexity solutions that can be employed in the aforemen-tioned wearable platforms. A typical state-of-the-art system utilizes Sigma Delta (Σ∆) ADCs incorporating a Σ∆ modulator and a decimation filter whereas the state-of-the-art decimation filters employ linear phase Finite-Impulse-Response (FIR) filters with high orders that in-crease the hardware complexity [1–5]. In this thesis, the novel use of minimum phase Infinite-Impulse-Response (IIR) decimators is proposed where the hardware complexity is massively reduced compared to the conventional FIR decimators. In addition, the non-linear phase effects of these filters are also investigated since phase non-linearity may distort the time domain representation of the signal being filtered which is un-desirable effect for biopotential signals especially when the fiducial characteristics carry diagnostic importance. In the case of ECG monitoring systems the effect of the IIR filter phase non-linearity is minimal which does not affect the diagnostic accuracy of the signals. The work undertaken also proposes two methods for reducing the hardware complexity of the popular biosignal processing tool, Discrete Wavelet Transform (DWT). General purpose multipliers are known to be hardware and power hungry in terms of the number of addition operations or their underlying building blocks like full adders or half adders required. Higher number of adders leads to an increase in the power consumption which is directly proportional to the clock frequency, supply voltage, switching activity and the resources utilized. A typical Field-Programmable-Gate-Array’s (FPGA) resources are Look-up Tables (LUTs) whereas a custom Digital Signal Processor’s (DSP) are gate-level cells of standard cell libraries that are used to build adders [6]. One of the proposed methods is the replacement of the hardware and power hungry general pur-pose multipliers and the coefficient memories with reconfigurable multiplier blocks that are composed of simple shift-add networks and multiplexers. This method substantially reduces the resource utilization as well as the power consumption of the system. The second proposed method is the design and implementation of the DWT filter banks using IIR filters which employ less number of arithmetic operations compared to the state-of-the-art FIR wavelets. This reduces the hardware complexity of the analysis filter bank of the DWT and can be employed in applications where the reconstruction is not required. However, the synthesis filter bank for the IIR wavelet transform has a higher computational complexity compared to the conventional FIR wavelet synthesis filter banks since re-indexing of the filtered data sequence is required that can only be achieved via the use of extra registers. Therefore, this led to the proposal of a novel design which replaces the complex IIR based synthesis filter banks with FIR fil-ters which are the approximations of the associated IIR filters. Finally, a comparative study is presented where the hybrid IIR/FIR and FIR/FIR wavelet filter banks are de-ployed in a typical noise reduction scenario using the wavelet thresholding techniques. It is concluded that the proposed hybrid IIR/FIR wavelet filter banks provide better denoising performance, reduced computational complexity and power consumption in comparison to their IIR/IIR and FIR/FIR counterparts

    Tree-structured complementary filter banks using all-pass sections

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    Tree-structured complementary filter banks are developed with transfer functions that are simultaneously all-pass complementary and power complementary. Using a formulation based on unitary transforms and all-pass functions, we obtain analysis and synthesis filter banks which are related through a transposition operation, such that the cascade of analysis and synthesis filter banks achieves an all-pass function. The simplest structure is obtained using a Hadamard transform, which is shown to correspond to a binary tree structure. Tree structures can be generated for a variety of other unitary transforms as well. In addition, given a tree-structured filter bank where the number of bands is a power of two, simple methods are developed to generate complementary filter banks with an arbitrary number of channels, which retain the transpose relationship between analysis and synthesis banks, and allow for any combination of bandwidths. The structural properties of the filter banks are illustrated with design examples, and multirate applications are outlined

    Low power, reduced complexity filtering and improved tracking accuracy for GNSS

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    This thesis addresses the power consumption problems resulting from the advent of multiple GNSS satellite systems which create the need for receivers supporting multi-frequency, multi-constellation GNSS systems. Such a multi-mode receiver requires a substantial amount of signal processing power which translates to increased hardware complexity and higher power dissipation which reduces the battery life of a mobile platform. During the course of the work undertaken, a power analysis tool was developed in order to be able to estimate the hardware utilisation as well as the power consumption of a digital system. By using the power estimation tool developed, it was established that most of the power was dissipated after the Analog to Digital Converter (ADC)by the filters associated with the decimation process. The power dissipation and the hardware complexity of the decimator can be reduced substantially by using a minimum-phase Infinite Impulse Response (IIR) filter. For Global Positioning System (GPS) civilian signals, the use of IIR filters does not deleteriously affect the positional accuracy. However, in the case where an IIR filter was deployed in a GLObalnaya NAvigatsionnaya Sputnikovaya Sistema (GLONASS) receiver, the pseudorange measurements of the receiver varied by up to 200 metres. The work undertaken proposes various methods that overcomes the pseudorange measurement variation and reports on the results that are on par with linear-phase Finite Impulse Response (FIR) filters. The work also proposes a modified tracking loop that is capable of tracking very low Doppler frequencies without decreasing the tracking performance

    Channelization for Multi-Standard Software-Defined Radio Base Stations

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    As the number of radio standards increase and spectrum resources come under more pressure, it becomes ever less efficient to reserve bands of spectrum for exclusive use by a single radio standard. Therefore, this work focuses on channelization structures compatible with spectrum sharing among multiple wireless standards and dynamic spectrum allocation in particular. A channelizer extracts independent communication channels from a wideband signal, and is one of the most computationally expensive components in a communications receiver. This work specifically focuses on non-uniform channelizers suitable for multi-standard Software-Defined Radio (SDR) base stations in general and public mobile radio base stations in particular. A comprehensive evaluation of non-uniform channelizers (existing and developed during the course of this work) shows that parallel and recombined variants of the Generalised Discrete Fourier Transform Modulated Filter Bank (GDFT-FB) represent the best trade-off between computational load and flexibility for dynamic spectrum allocation. Nevertheless, for base station applications (with many channels) very high filter orders may be required, making the channelizers difficult to physically implement. To mitigate this problem, multi-stage filtering techniques are applied to the GDFT-FB. It is shown that these multi-stage designs can significantly reduce the filter orders and number of operations required by the GDFT-FB. An alternative approach, applying frequency response masking techniques to the GDFT-FB prototype filter design, leads to even bigger reductions in the number of coefficients, but computational load is only reduced for oversampled configurations and then not as much as for the multi-stage designs. Both techniques render the implementation of GDFT-FB based non-uniform channelizers more practical. Finally, channelization solutions for some real-world spectrum sharing use cases are developed before some final physical implementation issues are considered

    Studies on Implementation of . . . High Throughput and Low Power Consumption

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    In this thesis we discuss design and implementation of frequency selective digital filters with high throughput and low power consumption. The thesis includes proposed arithmetic transformations of lattice wave digital filters that aim at increasing the throughput and reduce the power consumption of the filter implementation. The thesis also includes two case studies where digital filters with high throughput and low power consumption are required. A method for obtaining high throughput as well as reduced power consumption of digital filters is arithmetic transformation of the filter structure. In this thesis arithmetic transformations of first- and second-order Richards’ allpass sections composed by symmetric two-port adaptors and implemented using carry-save arithmetic are proposed. Such filter sections can be used for implementation of lattice wave digital filters and bireciprocal lattice wave digital filters. The latter structures are efficient for implementation of interpolators and decimators by factors of two. Th

    Channelization Techniques For Wideband Radios

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    University of Minnesota Ph.D. dissertation. May 2017. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); x, 110 pages.From the very start of mobile communications, wireless data traffic volume and the number of applications have increased continuously and this continued increase will eventually necessitate the use of wider signal bandwidths by the fundamental constraints imposed by Shannon’s theorem. Additionally, the air channel is a common limited resource that is shared by all users and applications. While this limited wireless resource has mostly been pre-allocated, the utilization at any given time is often very low. For this environment, cognitive radio and carrier aggregation are potential solutions. Both cognitive radio and carrier aggregation require the processing of wideband signals unlike what is normally the focus of conventional narrow band receivers. This, in turn, makes it necessary to design receivers with a large BW and high dynamic range, and these conflicting requirements typically form the bottleneck in existing systems. Here, we discuss channelization techniques using an analog FFT (fast Fourier transform) to solve the bottleneck. First, a fully integrated hybrid filter bank ADC using an analog FFT is presented. The proposed structure enables the signals in each channel of a wideband system to be separately digitized using the full dynamic range of the ADC, so the small signals in wideband can benefit in terms of lowered quantization noise while accommodating large in-band signals. The prototype which is implemented in TSMC’s 40nm CMOS GP process with VGA gains ranging from 1 to 4 shows 90.4mW total power consumption for both the analog and digital sections. Second, analog polyphase-FFT technique is introduced. Polyphase-FFT allows for low power implementations of high performance multi-channel filter banks by utilizing computation sharing not unlike a standard FFT. Additionally, it enables a longer “effective window length” than is possible in a standard FFT. This characteristic breaks the trade-off between the main-lobe width and the side-lobe amplitudes in normal finite impulse response (FIR) filters. The 4-channel I/Q prototype is implemented in TSMC’s 65nm GP technology. The measured trans- fer function shows >38dB side-lobe suppression at 1GS/s operation. The average measured IIP3 is +25dBm differential power and the total integrated output noise is 208µVrms. The total power consumption for the polyphase-FFT filter bank (8- channels total) is 34.6mW (34.6pJ/conv)
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