Design and modelling of variability tolerant on-chip communication structures for future high performance system on chip designs

The incessant technology scaling has enabled the integration of functionally complex System-on-Chip (SoC) designs with a large number of heterogeneous systems on a single chip. The processing elements on these chips are integrated through on-chip communication structures which provide the infrastructure necessary for the exchange of data and control signals, while meeting the strenuous physical and design constraints. The use of vast amounts of on chip communications will be central to future designs where variability is an inherent characteristic. For this reason, in this thesis we investigate the performance and variability tolerance of typical on-chip communication structures. Understanding of the relationship between variability and communication is paramount for the designers; i.e. to devise new methods and techniques for designing performance and power efficient communication circuits in the forefront of challenges presented by deep sub-micron (DSM) technologies. The initial part of this work investigates the impact of device variability due to Random Dopant Fluctuations (RDF) on the timing characteristics of basic communication elements. The characterization data so obtained can be used to estimate the performance and failure probability of simple links through the methodology proposed in this work. For the Statistical Static Timing Analysis (SSTA) of larger circuits, a method for accurate estimation of the probability density functions of different circuit parameters is proposed. Moreover, its significance on pipelined circuits is highlighted. Power and area are one of the most important design metrics for any integrated circuit (IC) design. This thesis emphasises the consideration of communication reliability while optimizing for power and area. A methodology has been proposed for the simultaneous optimization of performance, area, power and delay variability for a repeater inserted interconnect. Similarly for multi-bit parallel links, bandwidth driven optimizations have also been performed. Power and area efficient semi-serial links, less vulnerable to delay variations than the corresponding fully parallel links are introduced. Furthermore, due to technology scaling, the coupling noise between the link lines has become an important issue. With ever decreasing supply voltages, and the corresponding reduction in noise margins, severe challenges are introduced for performing timing verification in the presence of variability. For this reason an accurate model for crosstalk noise in an interconnection as a function of time and skew is introduced in this work. This model can be used for the identification of skew condition that gives maximum delay noise, and also for efficient design verification

Superconducting flux qubits for high-connectivity quantum annealing without lossy dielectrics

Quantum annealing can potentially be used to find better solutions to hard optimization problems faster than purely classical hardware. To take full advantage of quantum effects such as tunneling, a physical annealer should be comprised of qubits with a sufficient degree of quantum coherence. In addition, to encode useful problems, an annealer should provide a dense physical connectivity graph between qubits. Towards these goals, we develop superconducting ``fluxmon'' flux qubits suitable for high-connectivity quantum annealing without the use of performance-degrading lossy dielectrics. We carry out in-depth studies of noise and dissipation, and of qubit-qubit coupling in the strongly nonlinear regime. We perform the first frequency-resolved measurements extracting both the quantum and classical parts of the 1/f flux noise intrinsic to superconducting devices, and observe the classical-to-quantum crossover of the noise. We also identify atomic hydrogen as a magnetic dissipation source. We then implement tunable inter-qubit coupling compatible with high connectivity, and provide direct spectroscopic measurements of ultra-strong coupling between qubits. Finally, we use our system to explore quantum annealing faster than the system thermalization time, a previously unaccessed regime

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Implantable Low-Noise Fiberless Optoelectrodes for Optogenetic Control of Distinct Neural Populations

The mammalian brain is often compared to an electrical circuit, and its dynamics and function are governed by communication across different types neurons. To treat neurological disorders like Alzheimer’s and Parkinson’s, which are characterized by inhibition or amplification of neural activity in a particular region or lack of communication between different regions of the brain, there is a need to understand troubleshoot neural networks at cellular or local circuit level. In this work, we introduce a novel implantable optoelectrode that can manipulate more than one neuron type at a single site, independently and simultaneously. By delivering multi-color light using a scalable optical waveguide mixer, we demonstrate manipulation of multiple neuron types at precise spatial locations in vivo for the first time. We report design, micro-fabrication and optoelectronic packaging of a fiber-less, multicolor optoelectrode. The compact optoelectrode design consists of a 7 μm x 30 μm dielectric optical waveguide mixer and eight electrical recording sites monolithically integrated on each shank of a 22 μm-thick four-shank silicon neural probe. The waveguide mixers are coupled to eight side-emitting injection laser diodes (ILDs) via gradient-index (GRIN) lenses assembled on the probe backend. GRIN-based optoelectrode enables efficient optical coupling with large alignment tolerance to provide wide optical power range (10 to 3000 mW/mm2 irradiance) at stimulation ports. It also keeps thermal dissipation and electromagnetic interference generated by light sources sufficiently far from the sensitive neural signals, allowing thermal and electrical noise management on a multilayer printed circuit board. We demonstrated device verification and validation in CA1 pyramidal layer of mice hippocampus in both anesthetized and awake animals. The packaged devices were used to manipulate variety of multi-opsin preparations in vivo expressing different combinations of Channelrhodopsin-2, Archaerhodopsin and ChrimsonR in pyramidal and parvalbumin interneuron cells. We show effective stimulation, inhibition and recording of neural spikes at precise spatial locations with less than 100 μV stimulation-locked transients on the recording channels, demonstrating novel use of this technology in the functional dissection of neural circuits.PHDBiomedical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137171/1/kkomal_1.pd

EUROSENSORS XVII : book of abstracts

Fundação Calouste Gulbenkien (FCG).Fundação para a Ciência e a Tecnologia (FCT)

Modeling EMI Resulting from a Signal Via Transition Through Power/Ground Layers

Signal transitioning through layers on vias are very common in multi-layer printed circuit board (PCB) design. For a signal via transitioning through the internal power and ground planes, the return current must switch from one reference plane to another reference plane. The discontinuity of the return current at the via excites the power and ground planes, and results in noise on the power bus that can lead to signal integrity, as well as EMI problems. Numerical methods, such as the finite-difference time-domain (FDTD), Moment of Methods (MoM), and partial element equivalent circuit (PEEC) method, were employed herein to study this problem. The modeled results are supported by measurements. In addition, a common EMI mitigation approach of adding a decoupling capacitor was investigated with the FDTD method