System level power integrity transient analysis using a physics-based approach

With decreasing supply voltage level and massive demanding current on system chipset, power integrity design becomes more and more critical for system stability. The ultimate goal of well-designed power delivery network (PDN) is to deliver desired voltage level from the source to destination, in other words, to minimize voltage noise delivered to digital devices. The thesis is composed of three parts. The first part focuses on-die level power models including simplified chip power model (CPM) for system level analysis and the worst scenario current profile. The second part of this work introduces the physics-based equivalent circuit model to simplify the passive PDN model to RLC circuit netlist, to be compatible with any spice simulators and tremendously boost simulation speed. Then a novel system/chip level end-to-end transient model is proposed, including the die model and passive PDN model discussed in previous two chapters as well as a SIMPLIS based small signal VRM model. In the last part of the thesis, how to model voltage regulator module (VRM) is explicitly discussed. Different linear approximated VRM modeling approaches have been compared with the SIMPLIS small signal VRM model in both frequency domain and time domain. The comparison provides PI engineers a guideline to choose specific VRM model under specific circumstances. Finally yet importantly, a PDN optimization example was given. Other than previous PDN optimization approaches, a novel hybrid target impedance concept was proposed in this thesis, in order to improve system level PDN optimization process --Abstract, page iv

Quantifiable Assurance: From IPs to Platforms

Hardware vulnerabilities are generally considered more difficult to fix than software ones because they are persistent after fabrication. Thus, it is crucial to assess the security and fix the vulnerabilities at earlier design phases, such as Register Transfer Level (RTL) and gate level. The focus of the existing security assessment techniques is mainly twofold. First, they check the security of Intellectual Property (IP) blocks separately. Second, they aim to assess the security against individual threats considering the threats are orthogonal. We argue that IP-level security assessment is not sufficient. Eventually, the IPs are placed in a platform, such as a system-on-chip (SoC), where each IP is surrounded by other IPs connected through glue logic and shared/private buses. Hence, we must develop a methodology to assess the platform-level security by considering both the IP-level security and the impact of the additional parameters introduced during platform integration. Another important factor to consider is that the threats are not always orthogonal. Improving security against one threat may affect the security against other threats. Hence, to build a secure platform, we must first answer the following questions: What additional parameters are introduced during the platform integration? How do we define and characterize the impact of these parameters on security? How do the mitigation techniques of one threat impact others? This paper aims to answer these important questions and proposes techniques for quantifiable assurance by quantitatively estimating and measuring the security of a platform at the pre-silicon stages. We also touch upon the term security optimization and present the challenges for future research directions

A Survey on Trust Metrics for Autonomous Robotic Systems

This paper surveys the area of Trust Metrics related to security for autonomous robotic systems. As the robotics industry undergoes a transformation from programmed, task oriented, systems to Artificial Intelligence-enabled learning, these autonomous systems become vulnerable to several security risks, making a security assessment of these systems of critical importance. Therefore, our focus is on a holistic approach for assessing system trust which requires incorporating system, hardware, software, cognitive robustness, and supplier level trust metrics into a unified model of trust. We set out to determine if there were already trust metrics that defined such a holistic system approach. While there are extensive writings related to various aspects of robotic systems such as, risk management, safety, security assurance and so on, each source only covered subsets of an overall system and did not consistently incorporate the relevant costs in their metrics. This paper attempts to put this prior work into perspective, and to show how it might be extended to develop useful system-level trust metrics for evaluating complex robotic (and other) systems

Where to restore ecological connectivity? Detecting barriers and quantifying restoration benefits

Landscape connectivity is crucial for many ecological processes, including dispersal, gene flow, demographic rescue, and movement in response to climate change. As a result, governmental and non-governmental organizations are focusing efforts to map and conserve areas that facilitate movement to maintain population connectivity and promote climate adaptation. In contrast, little focus has been placed on identifying barriers—landscape features which impede movement between ecologically important areas—where restoration could most improve connectivity. Yet knowing where barriers most strongly reduce connectivity can complement traditional analyses aimed at mapping best movement routes. We introduce a novel method to detect important barriers and provide example applications. Our method uses GIS neighborhood analyses in conjunction with effective distance analyses to detect barriers that, if removed, would significantly improve connectivity. Applicable in least-cost, circuit-theoretic, and simulation modeling frameworks, the method detects both complete (impermeable) barriers and those that impede but do not completely block movement. Barrier mapping complements corridor mapping by broadening the range of connectivity conservation alternatives available to practitioners. The method can help practitioners move beyond maintaining currently important areas to restoring and enhancing connectivity through active barrier removal. It can inform decisions on trade-offs between restoration and protection; for example, purchasing an intact corridor may be substantially more costly than restoring a barrier that blocks an alternative corridor. And it extends the concept of centrality to barriers, highlighting areas that most diminish connectivity across broad networks. Identifying which modeled barriers have the greatest impact can also help prioritize error checking of land cover data and collection of field data to improve connectivity maps. Barrier detection provides a different way to view the landscape, broadening thinking about connectivity and fragmentation while increasing conservation options

Exploration of Digital Circuits and Transistor-Level Testing in the DARPA TRUST Program

The need to verify correct circuit operation has grown in recent years due to adversaries ability to compromise DoD systems. The DARPA program addressed this issue and implemented the DARPA TRUST program to verify untrusted circuits using software. The DARPA TRUST program was initiated in 2006 and due to this the limitations and potential errors in the program have not yet been fully explored. This research identifies the potential errors in the program by conducting transistor-level testing on circuits. The DARPA TRUST program currently operates at the gate-level and conducting various experiments at the transistor- level brought to light potential problems with current DARPA TRUST testing. The way that transistor-level verification is conducted is through netlist matching. A schematic of a circuit is created and the netlist is extracted, after that a metal layout of a circuit is created and the netlist is extracted. Once the two netlists are extracted, a matching program is used and the result determines if the verification process is successful. Parasitic capacitance was extracted in the metal layout version of a circuit and netlists were compared with the schematic version. Results show that parasitic capacitance is overlooked in the DARPA TRUST program even though this could potentially cause a fabricated device to fail. Transmission lines were simulated by creating metal wiring between two inverters. These metal lines mimic the operation of a transmission line. These transmission lines were experimented on and it was determined that the DARPA TRUST program does not effectively check for potential errors in transmission line fabrication. The results of this research brought to light the vulnerabilities in the DARPA TRUST program and addressed the need for the program to conduct transistor-level testing

Teledesic : a product, process, and supply chain design methodology

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science; and, (S.M.)--Massachusetts Institute of Technology, Sloan School of Management, 1998.Includes bibliographical references (leaf 44).by Lance Clifford Mansfield.S.M

Continual improvement: A bibliography with indexes, 1992-1993

This bibliography lists 606 references to reports and journal articles entered into the NASA Scientific and Technical Information Database during 1992 to 1993. Topics cover the philosophy and history of Continual Improvement (CI), basic approaches and strategies for implementation, and lessons learned from public and private sector models. Entries are arranged according to the following categories: Leadership for Quality, Information and Analysis, Strategic Planning for CI, Human Resources Utilization, Management of Process Quality, Supplier Quality, Assessing Results, Customer Focus and Satisfaction, TQM Tools and Philosophies, and Applications. Indexes include subject, personal author, corporate source, contract number, report number, and accession number

On-Chip Digital Decoupling Capacitance Methodology

Signal integrity has become a major problem in digital IC design. One cause of this problem is device scaling which results in a sharp reduction of supply voltage, creating stringent noise margin requirements to ensure functionality. Reductions in feature size also result in increased clock speeds leading to many different high frequency noise producing components. As on-chip area increases to allow for more computational capability, so does the amount of digital logic to be placed, magnifying the effects of noisy interconnect structures. Supply noise, modeled as AV = Ldi/dt , is caused by rapid current spikes during a rise or fall time. Decoupling capacitors often fill empty on-chip space for the purpose of limiting this noise. This work introduces a novel methodology that attempts to quantify and locate decoupling capacitors within a power distribution network. The bondwire attached on the periphery of the face of the die is taken to be the dominant source of inductance. It is shown that distributing capacitance closer to the switching elements is most effective at reducing supply noise. A chip has been designed using TSMC 90 nm technology that implements the ideas presented in this work. Simulation results show that noise fluctuations are high enough such that random placement of decoupling capacitance is not effective for large digital structures. The amount of interconnect generated on-chip noise increases with area, resulting in the need for an optimal decoupling scheme. As scaling continues, supply voltages and noise margins will decrease, creating the need for a robust decoupling capacitance methodology

A wireless system for crack monitoring in concrete structures

The formation of cracks in concrete is a normal phenomenon. However, effective control and prevention of the formation of cracks is the key for successful life of concrete structures. Specifically, cracks represent a path of least resistance for moisture and corrosive ionic agents from de-icing salts to reach embedded steel in concrete. Commercial wireless sensor networks utilizing crack gauge sensors can be applied for crack monitoring in the common concrete structure. The crack sensors circuits\u27 boards, which are used to stimulate the cracks, are currently unavailable for the SG-Link module platform. The SG-Link module is an ultra-low-power module for use in sensor networks, monitoring applications and rapid application prototyping. Therefore, a crack sensor circuit board for the SG-Link module platform has been developed. The development of a smart wireless sensor network for the crack monitoring system is divided into four parts: a crack gauge sensor, signal conditioning, the SG-Link module, and a base station unit. The signal conditioning module consists of a crack gauge sensor, a wheatstone bridge, an amplifier, and a filter. The SG-Link module consists of an analog to digital converter (ADC), a microcontroller unit (MCC), and a transmitter with an antenna. The base station unit includes an antenna and a receiver module connected to the base station or computer. In this study, cracks are monitored based on the change of the electrical resistance between the sensor\u27s two terminals that are taken from the simulation model of the crack sensor board consisting of a crack gauge sensor and signal conditioning. This thesis looked at the effectiveness of a wireless system for crack monitoring in concrete structures. Tests were conducted in a laboratory to monitor the cracks in the structures and explore the validity and reliability of the monitoring mechanism and data transmission

An approach to quantifying hardware diversity against common cause failures

In this thesis, we cover the gapof quantifying diversity by introducing DIMP, a low-cost diversity metric based on analyzing the paths of the circuits and relating it to the particular case of automotive microcontrollers that implement lockstep cores