End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures

Enabling More than Moore: Accelerated Reliability Testing and Risk Analysis for Advanced Electronics Packaging

For five decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in miniaturization of electronics products-Moore's Law. Now, scaling hits a brick wall, a paradigm shift. The industry roadmaps recognized the scaling limitation and project that packaging technologies will meet further miniaturization needs or ak.a "More than Moore". This paper presents packaging technology trends and accelerated reliability testing methods currently being practiced. Then, it presents industry status on key advanced electronic packages, factors affecting accelerated solder joint reliability of area array packages, and IPC/JEDEC/Mil specifications for characterizations of assemblies under accelerated thermal and mechanical loading. Finally, it presents an examples demonstrating how Accelerated Testing and Analysis have been effectively employed in the development of complex spacecraft thereby reducing risk. Quantitative assessments necessarily involve the mathematics of probability and statistics. In addition, accelerated tests need to be designed which consider the desired risk posture and schedule for particular project. Such assessments relieve risks without imposing additional costs. and constraints that are not value added for a particular mission. Furthermore, in the course of development of complex systems, variances and defects will inevitably present themselves and require a decision concerning their disposition, necessitating quantitative assessments. In summary, this paper presents a comprehensive view point, from technology to systems, including the benefits and impact of accelerated testing in offsetting risk

MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS

This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due tothe breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies

Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap

The objective of this document is to update the NASA roadmap on packaging technologies (initially released in 2007) and to present the current trends toward further reducing size and increasing functionality. Due to the breadth of work being performed in the area of microelectronics packaging, this report presents only a number of key packaging technologies detailed in three industry roadmaps for conventional microelectronics and a more recently introduced roadmap for organic and printed electronics applications. The topics for each category were down-selected by reviewing the 2012 reports of the International Technology Roadmap for Semiconductor (ITRS), the 2013 roadmap reports of the International Electronics Manufacturing Initiative (iNEMI), the 2013 roadmap of association connecting electronics industry (IPC), the Organic Printed Electronics Association (OE-A). The report also summarizes the results of numerous articles and websites specifically discussing the trends in microelectronics packaging technologies

OPTIMIZATION OF SURFACE MOUNT TECHNOLOGY SPECIALIZING IN HEAT DISSIPATION IN BGA CSPs

This project describes heat dissipation and mechanical deformation in BGAs. In contemporary industries, demand for smaller packages has increased the concern of thermal management. The lead-free movement has altered the properties of BGAs and comes with its own set of concerns. Packages were simulated and analyzed thermo-electrically using CAD and ANSYS software. The goal was to improve thermal management of electrical loads in CSP BGAs. Lead-based solder simulations demonstrated higher reliability than lead-free alternatives. Results indicate that maximum temperature and stresses were concentrated at the perimeter, especially the corners. This project resulted in suggestions for improvements for existing packaging and opportunities for future projects

MODELING RATE DEPENDENT DURABILITY OF LOW-Ag SAC INTERCONNECTS FOR AREA ARRAY PACKAGES UNDER TORSION LOADS

The thesis discusses modeling rate-dependent durability of solder interconnects under mechanical torsion loading for surface mount area array components. The study discusses an approach to incorporate strain-rate dependency in durability estimation for solder interconnects. The components under study are two configurations of BGAs (ball grid array) assembled with select lead-free solders. A torsion test setup is used to apply displacement controlled loads on the test board. Accelerated test load profile is experimentally determined. Torsion test is carried out for all the components under investigation to failure. Strain-rate dependent (Johnson-Cook model) and strain-rate independent, elastic-plastic properties are used to model the solders in finite element simulation. Damage model from literature is used to estimate the durability for SAC305 solder to validate the approach. Test data is used to extract damage model constants for SAC105 solder and extract mechanical fatigue durability curve

Reliability of CGA/LGA/HDI Package Board/Assembly (Revision A)

This follow-up report presents reliability test results conducted by thermal cycling of five CGA assemblies evaluated under two extreme cycle profiles, representative of use for high-reliability applications. The thermal cycles ranged from a low temperature of 55 C to maximum temperatures of either 100 C or 125 C with slow ramp-up rate (3 C/min) and dwell times of about 15 minutes at the two extremes. Optical photomicrographs that illustrate key inspection findings of up to 200 thermal cycles are presented. Other information presented include an evaluation of the integrity of capacitors on CGA substrate after thermal cycling as well as process evaluation for direct assembly of an LGA onto PCB. The qualification guidelines, which are based on the test results for CGA/LGA/HDI packages and board assemblies, will facilitate NASA projects' use of very dense and newly available FPGA area array packages with known reliably and mitigation risks, allowing greater processing power in a smaller board footprint and lower system weight

A THERMOMECHANICAL FATIGUE LIFE PREDICTION METHODOLOGY FOR BALL GRID ARRAY COMPONENTS WITH REWORKABLE UNDERFILL

Underfill materials were originally developed to improve the thermo-mechanical reliability of flip-chip devices due to the large coefficient of thermal expansion (CTE) mismatch between the silicon die and substrate. More recently, underfill materials, specifically reworkable underfills, have been used to improve reliability of second level interconnects in ball grid array (BGA) packages in harsh end-use environments such as automotive, military and aerospace. In these environments, electronic components are exposed to mechanical shock, vibration, and large fluctuations in temperatures. Although reworkable underfills improve the reliability of BGA components under mechanical shock and vibration, some reworkable underfills have been shown to reduce reliability during thermal cycling environments. Consequently, this research employs experimental and numerical approaches to investigate the impact of reworkable underfill materials on thermomechanical fatigue life of solder joints in BGA packages. In the first section of the analysis, material characterization of a reworkable underfill is performed to determine appropriate material models for reworkable underfills. In the second analysis section, a variety of underfill materials with different properties are exposed to harsh and benign thermal cycles to determine the stress state responsible for reducing fatigue life of solder joints in BGA packages. In the final analysis section, simulations are performed on the BGAs with reworkable underfill to develop a fatigue life predication methodology that implements a modified mode separation scheme. The model developed in this work provides a working fatigue life approach for BGA packages with reworkable underfills exposed to thermal loading. The results of this study can be utilized by the automotive, military, and aerospace industries to optimize underfill material selection process and provide reliability assessment of BGA components in real world environments

TEMPERATURE CYCLING RELIABILITY OF REBALLED AND REWORKED BALL GRID ARRAY PACKAGES IN SNPB AND SAC ASSEMBLY

In recent years, many countries banned the use of lead in select high volume electronic equipment. However, exemptions from lead-free legislation have been granted for certain products, especially those intended for high-reliability applications. Manufacturers with exemption are facing dwindling supply of lead-based components for their products. This change has left many high-reliability electronic equipment manufacturers with the choices of, mixing lead-free components in tin-lead assembly process, converting products to lead-free, or reprocessing lead-free components to comply with the tin-lead assembly process. Reballing has been used for component reclamation, but right now it offers a way to reprocess the ball grid array packages. The reliability of reballed BGA assembly needs to be determined before the implementation. Mixing lead-free ball grid array packages with eutectic tin-lead solder paste bring new challenges to the current electronic industry. The mixed assemblies with long-term reliability need to be investigated. Although rework has been implemented for decades, the impact of multiple rework process on the reliability of lead-free and mixed assemblies is still unknown. Lead-free ball grid array packages with Sn3.0Ag0.5Cu solder balls were subjected to the reballing process. Ball shear test and cold bump pull test were used to investigate the solder ball attachment strength of the reballed BGAs. Temperature cycling test was used to evaluate the temperature cycling reliability of reballed tin-lead, lead-free and mixed assemblies. The solder ball strength and the temperature cycling reliability of reballed components were independent of the reballing method. The temperature cycling reliability of mixed assemblies was equivalent to that of lead-free assemblies. Microstructure differences in lead-free, mixed and reballed tin-lead assemblies were investigated to explain the temperature cycling reliability results. Lead-free and mixed assemblies were subjected to the rework process. Temperature cycling test was used to evaluate the temperature cycling reliability of reworked assemblies. Cu over-consumption, Cu pad dissolution and thick interfacial intermetallic layer were found in the reworked assemblies. Microstructural investigation and geometry analysis were used to analyze the temperature cycling reliability degradation in the reworked assemblies after multiples rework processes

Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies

Working for the photolithography tool manufacturer leader sometimes gives me the impression of how complex and specific is the sector I am working on. This master thesis topic came with the goal of getting the overall picture of the state-of-the-art: stepping out and trying to get a helicopter view usually helps to understand where a process is in the productive chain, or what other firms and markets are doing to continue improvingUniversidad de sevilla.Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico