Introduction to Surface-Mount Technology

In chapter 1, the surface-mount technology and reflow soldering technology are overviewed. A brief introduction is presented into the type of electronic components, including through-hole- and surface-mounted ones. Steps of reflow soldering technology are outlined, and details are given regarding the properties of solder material in this technology. The rheological behavior of solder pastes is detailed, and some recent advancements in addressing the thixotropic behavior of this material are summarized. The process of stencil printing is detailed next, which is the most crucial step in reflow soldering technology; since even 60–70% of the soldering failures can be traced back to this process. The topic includes the structures of stencils, discussion of the primary process parameters, and process optimization possibilities by numerical modeling. Process issues of component placement are presented. The critical parameter (process and machines capability), which is used extensively for characterizing the placement process is studied. In connection with the measurement of process capability, the method of Gage R&R (repeatability and reproducibility) is detailed, including the estimation of respective variances. Process of the reflow soldering itself is detailed, including the two main phenomena taking place when the solder is in the molten state, namely: wetting of the liquid solder due to surface tension, and intermetallic compound formation due to diffusion. Solder profile calculation and component movements during the soldering (e.g., self-alignment of passive components) are presented too. Lastly, the pin-in-paste technology (reflow solder of through-hole components) is detailed, including some recent advancements in the optimization of this technology by utilizing machine learning techniques

JTEC Panel report on electronic manufacturing and packaging in Japan

This report summarizes the status of electronic manufacturing and packaging technology in Japan in comparison to that in the United States, and its impact on competition in electronic manufacturing in general. In addition to electronic manufacturing technologies, the report covers technology and manufacturing infrastructure, electronics manufacturing and assembly, quality assurance and reliability in the Japanese electronics industry, and successful product realization strategies. The panel found that Japan leads the United States in almost every electronics packaging technology. Japan clearly has achieved a strategic advantage in electronics production and process technologies. Panel members believe that Japanese competitors could be leading U.S. firms by as much as a decade in some electronics process technologies

NASA Innovative Advanced Concepts (NIAC) Phase 1 Final Report: Venus Landsailer Zephyr

Imagine sailing across the hot plains of Venus! A design for a craft to do just this was completed by the COncurrent Multidisciplinary Preliminary Assessment of Space Systems (COMPASS) Team for the NASA Innovative Advanced Concepts (NIAC) project. The robotic craft could explore over 30 km of surface of Venus, driven by the power of the wind

Superconducting flux circuits for coherent quantum annealing

Quantum annealing is a method with the potential to solve hard optimization problems faster than any classical method. In the near term, quantum annealing is particularly appealing due to its low control requirement, relative to gate-based quantum computation. However, despite the fact that large-scale quantum annealers containing more than 5000 qubits have been made commercially available, identifying a quantum advantage for practical problems has remained an elusive target. Amongst other issues, poor coherence is considered the main prohibitive factor for these annealers to take on the quest for quantum advantage. In this thesis, we make progress in realizing a highly coherent quantum annealer, based on superconducting capacitively-shunted flux qubits (CSFQ). First, we are met with the challenge of crosstalk calibration when implementing individual control of the qubits and couplers in the annealer, which is important for exploring novel annealing protocols. Two different methods, relying on the symmetries of the superconducting circuits, are proposed and successfully implemented to tackle this challenge. Second, we experimentally demonstrate long-range correlation in a chain of couplers, which enables effective coupling of qubits over large distances. The coupler chain could be expanded to a coupler network to support high qubit connectivity, a highly desirable feature when embedding practical-scale optimization problems into the annealer hardware. Finally, we evaluate the noise properties of the CSFQ. Coherence time measurements reveal that the dominant noise in the system is intrinsic flux noise in the two control loops of the qubit. Landau-Zener transition, a toy model for quantum annealing, is investigated in a CSFQ, revealing a crossover from the weak to strong coupling to the environment. This crossover regime was not studied before in either theory or experiment, and we present a phenomenological spin bath model to elucidate this regime

Superconducting qubits for quantum annealing applications

Over the last two decades, Quantum Annealing (QA) has grown to be a commercial technology with machines reaching the scale of 5000 interconnected qubits. Two reasons for this progress are the relative ease of implementing adiabatic Hamiltonian control and QA’s partial robustness against errors caused by decoherence. Despite the success of this approach to quantum computation, proving a scaling advantage over classical computation remains an elusive goal to this date. Different strategies are therefore being considered to boost the performance of quantum annealing. These include using more coherent qubit architectures and error-suppression to limit the effect of environmental noise, implementing non-stoquastic driver terms and tailored annealing schedules to enhance the success probability of the algorithm, and using many-body couplers to embed higher-order binary optimisation problems with less resource overhead. This thesis contributes to these efforts in two different ways. The first part provides a detailed numerical analysis and a physical layout for a threebody coupler for flux qubits based on ancillary spins. The application of the coupler in a coherence-signature QA Hamiltonian is also considered and the results of the simulated quantum evolution are compared to the outcomes of classical optimisation on the problem Hamiltonian showing that the classical algorithms cannot correctly reproduce the state distribution at the end of QA. In the second part of the thesis, we develop a numerical method for mapping the Hamiltonian of a composite superconducting circuit to an effective many-qubit Hamiltonian. By overcoming drawbacks of standard reduction methods, this protocol can be used to guide the design of non-stoquastic and many-body Hamiltonian terms, as well as to get a more precise evaluation of the QA schedule parameters, which can greatly improve the outcomes of the optimisation. This numerical work is accompanied by a proposal for an experimental verification of the predictions of the reduction protocol and by some preliminary experimental results

Design of thermal control systems for testing of electronics

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2001.Includes bibliographical references (p. 239-242).In the electronic component manufacturing industry, most components are subjected to a full functional test before they are sold. Depending on the type of components, these functional tests may be performed at room temperature, at cold temperature, or at high temperature (-50C to 1600C) depending on the type of component and intended market. The thermal management of these components during testing forms two basic issues that need to be addressed. The first issue is the heating or cooling of devices to the desired temperature prior to being tested, and the second issue concerns temperature control during the actual functional test. This thesis covers the design, modeling and testing of two prototype systems. One system uses a low cost IR heating system to preheat bulk devices to a target temperature, prior to the actual functional test. Theory shows that the limits on temperature ramp rates are imposed by the device package configuration and carrier configuration. The results from the prototype system show that the IR heating chamber is an effective low cost, low volume system for uniformly heating a wide range of device and carrier types. The second prototype system uses high performance jet impingement coupled with laser heating to actively control the temperature of a high power density device during a functional test. Experimental results from the prototype system are presented and design guidelines for future systems are developed. The theory for temperature control is developed and the effects of package design and test sequence design on the temperature control limits are studied.by Matthew Sweetland.Ph.D

Venus Landsailer Zephyr

Imagine sailing across the hot plains of Venus! A design for a craft to do just this was completed by the COncurrent Multidisciplinary Preliminary Assessment of Space Systems (COMPASS) Team for the NASA Innovative Advanced Concepts (NIAC) project. The robotic craft could explore over 30 kilometers of the surface of Venus, driven by the power of the wind. The Zephyr Venus Landsailer is a science mission concept for exploring the surface of Venus with a mobility and science capability roughly comparable to the Mars Exploration Rovers (MER) mission, but using the winds of the thick atmosphere of Venus for propulsion. It would explore the plains of Venus in the year 2025, near the Venera 10 landing site, where wind velocities in the range of 80 to 120 centimeters per second (cm/s) were measured by earlier Soviet landing missions. These winds are harnessed by a large wing/sail which would also carry the solar cells to generate power. At around 250 kilograms (kg), Zephyr would carry an 8 meter tall airfoil sail (12 square meters area), 25 kg of science equipment (mineralogy, grinder, and weather instruments) and return 2 gigabytes of science over a 30 day mission. Due to the extreme temperatures (450 degrees Centigrade) and pressures (90 bar) on Venus, Zephyr would have only basic control systems (based on high temperature silicon carbide (SiC)electronics) and actuators. Control would come from an orbiter which is in turn controlled from Earth. Due to the time delay from the Earth a robust control system would need to exist on the orbiter to keep Zephyr on course. Data return and control would be made using a 250 megahertz link with the orbiter with a maximum data rate of 2 kilobits per second. At the minimal wind speed required for mobility of 35 cm/s, the vehicle move at a slow but steady 4 cm/s by positioning the airfoil and use of one wheel that is steered for pointing control. Navigation commands from the orbiter will be based upon navigation cameras, simple accelerometers and stability sensors; Zephyr's stability is robust, using a wide wheel base along with controls to "feather" or "luff" the airfoil and apply brakes to stop the vehicle in the case of unexpected conditions. This would be the science gathering configuration. The vehicle itself would need to be made from titanium (Ti) as the structural material, with a corrosion-barrier overcoating due to extreme temperatures on the surface

Rapid Assessment of BGA Fatigue Life Under Vibration Loading

Ball Grid Array (BGA) packages are a relatively new package type and have rapidly become the package style of choice. Much high density, high I/O count semiconductor devices are now only offered in this package style. Designers are naturally concerned about the robustness of BGA packages in a vibration environment when their experience base is with products using more traditional compliant gull or J leaded surface mount packages. Because designers simply do not have the experience, tools are needed to assess the vibration fatigue life of BGA packages during early design stages and not have to wait for product qualification testing, or field returns, to determine if a problem exists. This dissertation emphasizes a rapid assessment methodology to determine fatigue life of BGA components. If time and money were not an issue, clearly one would use a general-purpose finite element program to determine the dynamic response of the printed wiring board in the vibration environment. Once the response of the board was determined, one would determine the location and value of the critical stress in the component of interest. Knowing the critical stress, one would estimate the fatigue life from a damage model. The time required building the FEA model, conducting the analysis, and post-process the results would take at least a few days to weeks. This is too time-consuming, except in the most critical applications. It is not a process that can be used in everyday design and what-if simulations. The rapid assessment approach proposed in this research focuses on a physics of failure type approach to damage analysis and involves global and local modeling to determine the critical stress in the component of interest. A fatigue damage model then estimates the life. Once implemented in software, i.e. the new version of CALCE_PWA, the entire fatigue life assessment is anticipated to be executed by an average engineer in real time and take only minutes to generate accurate results

Printed Circuit Board Inspection and Quality Control - PCB Failure Causes and Cures

This two day workshop will discuss a range of topics, including root cause analysis, physics-of-failure principles and failure mechanisms in printed circuit boards. Printed circuit boards (PCBs) are the baseline for electronics manufacturing upon which electronic components are mounted and formed into electronic systems. PCBs are used in a variety of electronic circuits from simple one-transistor amplifiers to large super computers. A PCB serves three main functions: 1) it provides the necessary mechanical support for the components in the circuit 2) it provides the necessary electrical interconnections, and 3) it bears some form of legend which identifies the components it carries. The failure modes on the PCBs can be categorized in a hierarchical structure, in which the mechanisms and causes are site or location dependant. Specimen preparation techniques, non-destructive and destructive analysis, and materials characterization will also be discussed. The first day of the workshop will present methodologies for identifying potential failure mechanisms in electronics based on the failure history and, systematic approaches to root cause analysis. The second day will cover failure analysis techniques geared towards various failure mechanisms, along with numerous component and PCB assembly failure analysis case studies that illustrate the techniques and analysis. Failure analysis case studies will be used to illustrate the techniques and analysis principles to arrive at the root cause(s) of field failures on printed circuit boards, active components, and assemblies