1,928 research outputs found
Effect and Compensation of Timing Jitter in Through-Wall Human Indication via Impulse Through-Wall Radar
Impulse through-wall radar (TWR) is considered as one of preferred choices for through-wall human indication due to its good penetration and high range resolution. Large bandwidth available for impulse TWR results in high range resolution, but also brings an atypical adversity issue not substantial in narrowband radars โ high timing jitter effect, caused by the non-ideal sampling clock at the receiver. The fact that impulse TWR employs very narrow pulses makes little jitter inaccuracy large enough to destroy the signal correlation property and then degrade clutter suppression performance. In this paper, we focus on the timing jitter impact on clutter suppression in through-wall human indication via impulse TWR. We setup a simple timing jitter model and propose a criterion namely average range profile (ARP) contrast is to evaluate the jitter level. To combat timing jitter, we also develop an effective compensation method based on local ARP contrast maximization. The proposed method can be implemented pulse by pulse followed by exponential average background subtraction algorithm to mitigate clutters. Through-wall experiments demonstrate that the proposed method can dramatically improve through-wall human indication performance
Time-of-flight CMOS ใคใกใผใธใปใณใตใซใใ้ซ็ฒพๅบฆใป้ซ้่ท้ขใคใกใผใธใณใฐใซ้ขใใ็ ็ฉถ
Tohoku Universityๅๅฃซ๏ผๅทฅๅญฆ๏ผthesi
๊ณ ์ ์๋ฆฌ์ผ ๋งํฌ๋ฅผ ์ํ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ๋ฅผ ๊ธฐ๋ฐ์ผ๋ก ํ๋ ์ฃผํ์ ํฉ์ฑ๊ธฐ
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022. 8. ์ ๋๊ท .In this dissertation, major concerns in the clocking of modern serial links are discussed. As sub-rate, multi-standard architectures are becoming predominant, the conventional clocking methodology seems to necessitate innovation in terms of low-cost implementation. Frequency synthesis with active, inductor-less oscillators replacing LC counterparts are reviewed, and solutions for two major drawbacks are proposed. Each solution is verified by prototype chip design, giving a possibility that the inductor-less oscillator may become a proper candidate for future high-speed serial links.
To mitigate the high flicker noise of a high-frequency ring oscillator (RO), a reference multiplication technique that effectively extends the bandwidth of the following all-digital phase-locked loop (ADPLL) is proposed. The technique avoids any jitter accumulation, generating a clean mid-frequency clock, overall achieving high jitter performance in conjunction with the ADPLL. Timing constraint for the proper reference multiplication is first analyzed to determine the calibration points that may correct the existent phase errors. The weight for each calibration point is updated by the proposed a priori probability-based least-mean-square (LMS) algorithm. To minimize the time required for the calibration, each gain for the weight update is adaptively varied by deducing a posteriori which error source dominates the others. The prototype chip is fabricated in a 40-nm CMOS technology, and its measurement results verify the low-jitter, high-frequency clock generation with fast calibration settling. The presented work achieves an rms jitter of 177/223 fs at 8/16-GHz output, consuming 12.1/17-mW power.
As the second embodiment, an RO-based ADPLL with an analog technique that addresses the high supply sensitivity of the RO is presented. Unlike prior arts, the circuit for the proposed technique does not extort the RO voltage headroom, allowing high-frequency oscillation. Further, the performance given from the technique is robust over process, voltage, and temperature (PVT) variations, avoiding the use of additional calibration hardware. Lastly, a comprehensive analysis of phase noise contribution is conducted for the overall ADPLL, followed by circuit optimizations, to retain the low-jitter output. Implemented in a 40-nm CMOS technology, the frequency synthesizer achieves an rms jitter of 289 fs at 8 GHz output without any injected supply noise. Under a 20-mVrms white supply noise, the ADPLL suppresses supply-noise-induced jitter by -23.8 dB.๋ณธ ๋
ผ๋ฌธ์ ํ๋ ์๋ฆฌ์ผ ๋งํฌ์ ํด๋ฝํน์ ๊ด์ฌ๋๋ ์ฃผ์ํ ๋ฌธ์ ๋ค์ ๋ํ์ฌ ๊ธฐ์ ํ๋ค. ์ค์๋, ๋ค์ค ํ์ค ๊ตฌ์กฐ๋ค์ด ์ฑํ๋๊ณ ์๋ ์ถ์ธ์ ๋ฐ๋ผ, ๊ธฐ์กด์ ํด๋ผํน ๋ฐฉ๋ฒ์ ๋ฎ์ ๋น์ฉ์ ๊ตฌํ์ ๊ด์ ์์ ์๋ก์ด ํ์ ์ ํ์๋ก ํ๋ค. LC ๊ณต์ง๊ธฐ๋ฅผ ๋์ ํ์ฌ ๋ฅ๋ ์์ ๋ฐ์ง๊ธฐ๋ฅผ ์ฌ์ฉํ ์ฃผํ์ ํฉ์ฑ์ ๋ํ์ฌ ์์๋ณด๊ณ , ์ด์ ๋ฐ์ํ๋ ๋๊ฐ์ง ์ฃผ์ ๋ฌธ์ ์ ๊ณผ ๊ฐ๊ฐ์ ๋ํ ํด๊ฒฐ ๋ฐฉ์์ ํ์ํ๋ค. ๊ฐ ์ ์ ๋ฐฉ๋ฒ์ ํ๋กํ ํ์
์นฉ์ ํตํด ๊ทธ ํจ์ฉ์ฑ์ ๊ฒ์ฆํ๊ณ , ์ด์ด์ ๋ฅ๋ ์์ ๋ฐ์ง๊ธฐ๊ฐ ๋ฏธ๋์ ๊ณ ์ ์๋ฆฌ์ผ ๋งํฌ์ ํด๋ฝํน์ ์ฌ์ฉ๋ ๊ฐ๋ฅ์ฑ์ ๋ํด ๊ฒํ ํ๋ค.
์ฒซ๋ฒ์งธ ์์ฐ์ผ๋ก์จ, ๊ณ ์ฃผํ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ๋์ ํ๋ฆฌ์ปค ์ก์์ ์ํ์ํค๊ธฐ ์ํด ๊ธฐ์ค ์ ํธ๋ฅผ ๋ฐฐ์ํํ์ฌ ๋ท๋จ์ ์์ ๊ณ ์ ๋ฃจํ์ ๋์ญํญ์ ํจ๊ณผ์ ์ผ๋ก ๊ทน๋ํ ์ํค๋ ํ๋ก ๊ธฐ์ ์ ์ ์ํ๋ค. ๋ณธ ๊ธฐ์ ์ ์งํฐ๋ฅผ ๋์ ์ํค์ง ์์ผ๋ฉฐ ๋ฐ๋ผ์ ๊นจ๋ํ ์ค๊ฐ ์ฃผํ์ ํด๋ฝ์ ์์ฑ์์ผ ์์ ๊ณ ์ ๋ฃจํ์ ํจ๊ป ๋์ ์ฑ๋ฅ์ ๊ณ ์ฃผํ ํด๋ฝ์ ํฉ์ฑํ๋ค. ๊ธฐ์ค ์ ํธ๋ฅผ ์ฑ๊ณต์ ์ผ๋ก ๋ฐฐ์ํํ๊ธฐ ์ํ ํ์ด๋ฐ ์กฐ๊ฑด๋ค์ ๋จผ์ ๋ถ์ํ์ฌ ํ์ด๋ฐ ์ค๋ฅ๋ฅผ ์ ๊ฑฐํ๊ธฐ ์ํ ๋ฐฉ๋ฒ๋ก ์ ํ์
ํ๋ค. ๊ฐ ๊ต์ ์ค๋์ ์ฐ์ญ์ ํ๋ฅ ์ ๊ธฐ๋ฐ์ผ๋กํ LMS ์๊ณ ๋ฆฌ์ฆ์ ํตํด ๊ฐฑ์ ๋๋๋ก ์ค๊ณ๋๋ค. ๊ต์ ์ ํ์ํ ์๊ฐ์ ์ต์ํ ํ๊ธฐ ์ํ์ฌ, ๊ฐ ๊ต์ ์ด๋์ ํ์ด๋ฐ ์ค๋ฅ ๊ทผ์๋ค์ ํฌ๊ธฐ๋ฅผ ๊ท๋ฉ์ ์ผ๋ก ์ถ๋ก ํ ๊ฐ์ ๋ฐํ์ผ๋ก ์ง์์ ์ผ๋ก ์ ์ด๋๋ค. 40-nm CMOS ๊ณต์ ์ผ๋ก ๊ตฌํ๋ ํ๋กํ ํ์
์นฉ์ ์ธก์ ์ ํตํด ์ ์์, ๊ณ ์ฃผํ ํด๋ฝ์ ๋น ๋ฅธ ๊ต์ ์๊ฐ์์ ํฉ์ฑํด ๋์ ํ์ธํ์๋ค. ์ด๋ 177/223 fs์ rms ์งํฐ๋ฅผ ๊ฐ์ง๋ 8/16 GHz์ ํด๋ฝ์ ์ถ๋ ฅํ๋ค.
๋๋ฒ์งธ ์์ฐ์ผ๋ก์จ, ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ๋์ ์ ์ ๋
ธ์ด์ฆ ์์กด์ฑ์ ์ํ์ํค๋ ๊ธฐ์ ์ด ํฌํจ๋ ์ฃผํ์ ํฉ์ฑ๊ธฐ๊ฐ ์ค๊ณ๋์๋ค. ์ด๋ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ์ ์ ํค๋๋ฃธ์ ๋ณด์กดํจ์ผ๋ก์ ๊ณ ์ฃผํ ๋ฐ์ง์ ๊ฐ๋ฅํ๊ฒ ํ๋ค. ๋์๊ฐ, ์ ์ ๋
ธ์ด์ฆ ๊ฐ์ ์ฑ๋ฅ์ ๊ณต์ , ์ ์, ์จ๋ ๋ณ๋์ ๋ํ์ฌ ๋ฏผ๊ฐํ์ง ์์ผ๋ฉฐ, ๋ฐ๋ผ์ ์ถ๊ฐ์ ์ธ ๊ต์ ํ๋ก๋ฅผ ํ์๋ก ํ์ง ์๋๋ค. ๋ง์ง๋ง์ผ๋ก, ์์ ๋
ธ์ด์ฆ์ ๋ํ ํฌ๊ด์ ๋ถ์๊ณผ ํ๋ก ์ต์ ํ๋ฅผ ํตํ์ฌ ์ฃผํ์ ํฉ์ฑ๊ธฐ์ ์ ์ก์ ์ถ๋ ฅ์ ๋ฐฉํดํ์ง ์๋ ๋ฐฉ๋ฒ์ ๊ณ ์ํ์๋ค. ํด๋น ํ๋กํ ํ์
์นฉ์ 40-nm CMOS ๊ณต์ ์ผ๋ก ๊ตฌํ๋์์ผ๋ฉฐ, ์ ์ ๋
ธ์ด์ฆ๊ฐ ์ธ๊ฐ๋์ง ์์ ์ํ์์ 289 fs์ rms ์งํฐ๋ฅผ ๊ฐ์ง๋ 8 GHz์ ํด๋ฝ์ ์ถ๋ ฅํ๋ค. ๋ํ, 20 mVrms์ ์ ์ ๋
ธ์ด์ฆ๊ฐ ์ธ๊ฐ๋์์ ๋์ ์ ๋๋๋ ์งํฐ์ ์์ -23.8 dB ๋งํผ ์ค์ด๋ ๊ฒ์ ํ์ธํ์๋ค.1 Introduction 1
1.1 Motivation 3
1.1.1 Clocking in High-Speed Serial Links 4
1.1.2 Multi-Phase, High-Frequency Clock Conversion 8
1.2 Dissertation Objectives 10
2 RO-Based High-Frequency Synthesis 12
2.1 Phase-Locked Loop Fundamentals 12
2.2 Toward All-Digital Regime 15
2.3 RO Design Challenges 21
2.3.1 Oscillator Phase Noise 21
2.3.2 Challenge 1: High Flicker Noise 23
2.3.3 Challenge 2: High Supply Noise Sensitivity 26
3 Filtering RO Noise 28
3.1 Introduction 28
3.2 Proposed Reference Octupler 34
3.2.1 Delay Constraint 34
3.2.2 Phase Error Calibration 38
3.2.3 Circuit Implementation 51
3.3 IL-ADPLL Implementation 55
3.4 Measurement Results 59
3.5 Summary 63
4 RO Supply Noise Compensation 69
4.1 Introduction 69
4.2 Proposed Analog Closed Loop for Supply Noise Compensation 72
4.2.1 Circuit Implementation 73
4.2.2 Frequency-Domain Analysis 76
4.2.3 Circuit Optimization 81
4.3 ADPLL Implementation 87
4.4 Measurement Results 90
4.5 Summary 98
5 Conclusions 99
A Notes on the 8REF 102
B Notes on the ACSC 105๋ฐ
Study of Layout Techniques in Dynamic Logic Circuitry for Single Event Effect Mitigation
Dynamic logic circuits are highly suitable for high-speed applications, considering the fact that they have a smaller area and faster transition. However, their application in space or other radiation-rich environments has been significantly inhibited by their susceptibility to radiation effects. This work begins with the basic operations of dynamic logic circuits, elaborates upon the physics underlying their radiation vulnerability, and evaluates three techniques that harden dynamic logic from the layout: drain extension, pulse quenching, and a proposed method. The drain extension method adds an extra drain to the sensitive node in order to improve charge sharing, the pulse quenching scheme utilizes charge sharing by duplicating a component that offsets the transient pulse, and the proposed technique takes advantage of both. Domino buffers designed using these three techniques, along with a conventional design as reference, were modeled and simulated using a 3D TCAD tool. Simulation results confirm a significant reduction of soft error rate in the proposed technique and suggest a greater reduction with angled incidence. A 130 nm chip containing designed buffer and register chains was fabricated and tested with heavy ion irradiation. According to the experiment results, the proposed design achieved 30% soft error rate reduction, with 19%, 20%, and 10% overhead in speed, power, and area, respectively
Full-Duplex Systems Using Multi-Reconfigurable Antennas
Full-duplex systems are expected to achieve 100% rate improvement over
half-duplex systems if the self-interference signal can be significantly
mitigated. In this paper, we propose the first full-duplex system utilizing
Multi-Reconfigurable Antenna (MRA) with ?90% rate improvement compared to
half-duplex systems. MRA is a dynamically reconfigurable antenna structure,
that is capable of changing its properties according to certain input
configurations. A comprehensive experimental analysis is conducted to
characterize the system performance in typical indoor environments. The
experiments are performed using a fabricated MRA that has 4096 configurable
radiation patterns. The achieved MRA-based passive self-interference
suppression is investigated, with detailed analysis for the MRA training
overhead. In addition, a heuristic-based approach is proposed to reduce the MRA
training overhead. The results show that at 1% training overhead, a total of
95dB self-interference cancellation is achieved in typical indoor environments.
The 95dB self-interference cancellation is experimentally shown to be
sufficient for 90% full-duplex rate improvement compared to half-duplex
systems.Comment: Submitted to IEEE Transactions on Wireless Communication
Recommended from our members
Circuits and architectures for the implementation of broadband channelizers
Broadband spectrum channelizers sub-divide a broadband input spectrum into multiple sub-bands, where each of the sub-bands is down-converted and further processed at baseband. These designs can help to relax baseband design specifications. For example, baseband analog-to-digital converters (ADCs) that process the sub-bands at the channelizer output see only a part of the incident spectrum. The sampling frequency, and potentially the dynamic range of each sub-band ADC can thus be relaxed, compared to the case where a single ADC is used to digitize the full spectrum.
Spectrum channelizers can be used for multiple applications. These designs can be used as general-purpose hybrid frequency-and-time domain ADCs. The designs can also be employed for spectrum analysis, as well as for wireless communication applications.
In this dissertation, two circuit techniques for the implementation of broadband channelizers are proposed. A frequency-translational feedback-based interference canceler for attenuating large interferers at the output of the front-end low-noise amplifier (LNA) of a channelizer is shown. The design uses harmonic rejection mixers (HRMs) with embedded frequency synthesis capability. While channelizers reduce the bandwidth and potentially the dynamic range of the baseband ADCs, the analog signal paths in the channelizer can be broadband. Consequently the dynamic range required of the analog section of a sub-band path can still be limited by the presence of large signals in other, potentially distant parts of the spectrum. The demonstrated design is useful for relaxing the dynamic range requirement of the analog section that follows the front-end LNA in a channelizer. Reduction of the harmonic response and the frequency synthesizer tuning-range is also achieved in this design.
Second, a two-stage HRM is proposed which shares the same bias current between the RF and baseband stages, thus reducing the power consumption. Issues arising from bias-current sharing, such as the 1/f noise of the RF stage and potential degradation of the 2nd harmonic response are identified, and circuit techniques are introduced to mitigate these potential degradation mechanisms.Electrical and Computer Engineerin
A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization
A new generation of radio telescopes is achieving unprecedented levels of
sensitivity and resolution, as well as increased agility and field-of-view, by
employing high-performance digital signal processing hardware to phase and
correlate large numbers of antennas. The computational demands of these imaging
systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the
number of independent beams, and N is the number of antennas. The
specifications of many new arrays lead to demands in excess of tens of PetaOps
per second.
To meet this challenge, we have developed a general purpose correlator
architecture using standard 10-Gbit Ethernet switches to pass data between
flexible hardware modules containing Field Programmable Gate Array (FPGA)
chips. These chips are programmed using open-source signal processing libraries
we have developed to be flexible, scalable, and chip-independent. This work
reduces the time and cost of implementing a wide range of signal processing
systems, with correlators foremost among them,and facilitates upgrading to new
generations of processing technology. We present several correlator
deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes
parameter application deployed on the Precision Array for Probing the Epoch of
Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31
pages. v2: corrected typo, v3: corrected Fig. 1
Analysis on the Influence of Synchronization Error on Fixed-filter Active Noise Control
The efficacy of active noise control technology in mitigating urban noise,
particularly in relation to low-frequency components, has been
well-established. In the realm of traditional academic research, adaptive
algorithms, such as the filtered reference least mean square method, are
extensively employed to achieve real-time noise reduction in many applications.
Nevertheless, the utilization of this technology in commercial goods is often
hindered by its significant computing complexity and inherent instability. In
this particular scenario, the adoption of the fixed-filter strategy emerges as
a viable alternative for addressing these challenges, albeit with a potential
trade-off in terms of noise reduction efficacy. This work aims to conduct a
theoretical investigation into the synchronization error of the digital Active
Noise Control (ANC) system. Keywords: Fixed-filter, Active noise control,
Multichannel active noise control
CMOS Quantum Computing: Toward A Quantum Computer System-on-Chip
Quantum computing is experiencing the transition from a scientific to an
engineering field with the promise to revolutionize an extensive range of
applications demanding high-performance computing. Many implementation
approaches have been pursued for quantum computing systems, where currently the
main streams can be identified based on superconducting, photonic, trapped-ion,
and semiconductor qubits. Semiconductor-based quantum computing, specifically
using CMOS technologies, is promising as it provides potential for the
integration of qubits with their control and readout circuits on a single chip.
This paves the way for the realization of a large-scale quantum computing
system for solving practical problems. In this paper, we present an overview
and future perspective of CMOS quantum computing, exploring developed
semiconductor qubit structures, quantum gates, as well as control and readout
circuits, with a focus on the promises and challenges of CMOS implementation
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