5 research outputs found

    Layout optimization in ultra deep submicron VLSI design

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    As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integration (VLSI) design. In this dissertation, we study several deep submicron problems (eg. coupling capacitance, antenna effect and delay variation) and propose optimization techniques to mitigate these DSM effects in the place-and-route stage of VLSI physical design. The place-and-route stage of physical design can be further divided into several steps: (1) Placement, (2) Global routing, (3) Layer assignment, (4) Track assignment, and (5) Detailed routing. Among them, layer/track assignment assigns major trunks of wire segments to specific layers/tracks in order to guide the underlying detailed router. In this dissertation, we have proposed techniques to handle coupling capacitance at the layer/track assignment stage, antenna effect at the layer assignment, and delay variation at the ECO (Engineering Change Order) placement stage, respectively. More specifically, at layer assignment, we have proposed an improved probabilistic model to quickly estimate the amount of coupling capacitance for timing optimization. Antenna effects are also handled at layer assignment through a linear-time tree partitioning algorithm. At the track assignment stage, timing is further optimized using a graph based technique. In addition, we have proposed a novel gate splitting methodology to reduce delay variation in the ECO placement considering spatial correlations. Experimental results on benchmark circuits showed the effectiveness of our approaches

    Studies on physical interconnect technologies in advanced SoC designs

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    制度:新 ; 文部省報告番号:甲1992号 ; 学位の種類:博士(工学) ; 授与年月日:2005/3/15 ; 早大学位記番号:新392

    Design Rules in VLSI Routing

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    One of the last major steps in the design of highly integrated circuits (VLSI design) is routing. The task of routing is to compute disjoint sets of wires connecting different parts of a chip in order to realize the desired electrical connectivity. Design rules define restrictions on the minimum distance and geometry of metal shapes. The intent of most design rules is to forbid patterns that cannot be manufactured well in the lithographic production process. This process has become extremely difficult with the current small feature sizes of 32 nm and below, which are still being manufactured using 193 nm wavelength technology. Because of this, the design rules of modern technologies have become very complex, and computing a routing with a sufficiently low number of design rule violations is a difficult task for automated routing tools. In this thesis we present in detail how design rules can be handled efficiently. We develop an appropriate design rule model which considerably reduces complexity while not being too restrictive. This involves mapping complex polygon-based rules to simpler rectangle-based rules and building equivalence classes of shapes with respect to their minimum distance requirements. Our model enables efficient checking of minimum distance rules, which has to be done dozens of times in each routing run. We also discuss efficient data structures that are necessary to achieve this. We implemented our design rule model within BonnRoute, the routing tool of the BonnTools, a software package for VLSI physical design developed at the Research Institute for Discrete Mathematics at the University of Bonn in cooperation with IBM. The result is a new module of BonnRoute, called BonnRoutRules, which computes this design rule model and embeds BonnRoute in the complex routing environment of current technologies. The BonnRouteRules module was a key part in enabling BonnRoute to route current 32 nm and 22 nm chips. We describe the combined routing flow used by IBM in practice, in which BonnRoute solves the main routing task and an industrial standard router is used for postprocessing. We present detailed experimental results of this flow on real-world designs. The results show that this combined flow produces routings with almost no remaining design rule violations, which proves that our design rule model works well in practice. Furthermore, compared to the industrial standard router alone, the combination with BonnRoute provides several significant benefits: It has 24% less runtime, 5% less wiring length, and over 90% less detours, which shows that with this flow we have an excellent routing tool in practice

    VLSI Routing for Advanced Technology

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    Routing is a major step in VLSI design, the design process of complex integrated circuits (commonly known as chips). The basic task in routing is to connect predetermined locations on a chip (pins) with wires which serve as electrical connections. One main challenge in routing for advanced chip technology is the increasing complexity of design rules which reflect manufacturing requirements. In this thesis we investigate various aspects of this challenge. First, we consider polygon decomposition problems in the context of VLSI design rules. We introduce different width notions for polygons which are important for width-dependent design rules in VLSI routing, and we present efficient algorithms for computing width-preserving decompositions of rectilinear polygons into rectangles. Such decompositions are used in routing to allow for fast design rule checking. A main contribution of this thesis is an O(n) time algorithm for computing a decomposition of a simple rectilinear polygon with n vertices into O(n) rectangles, preseverving two-dimensional width. Here the two-dimensional width at a point of the polygon is defined as the edge length of a largest square that contains the point and is contained in the polygon. In order to obtain these results we establish a connection between such decompositions and Voronoi diagrams. Furthermore, we consider implications of multiple patterning and other advanced design rules for VLSI routing. The main contribution in this context is the detailed description of a routing approach which is able to manage such advanced design rules. As a main algorithmic concept we use multi-label shortest paths where certain path properties (which model design rules) can be enforced by defining labels assigned to path vertices and allowing only certain label transitions. The described approach has been implemented in BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics, University of Bonn, in cooperation with IBM. We present experimental results confirming that a flow combining BonnRoute and an external cleanup step produces far superior results compared to an industry standard router. In particular, our proposed flow runs more than twice as fast, reduces the via count by more than 20%, the wiring length by more than 10%, and the number of remaining design rule errors by more than 60%. These results obtained by applying our multiple patterning approach to real-world chip instances provided by IBM are another main contribution of this thesis. We note that IBM uses our proposed combined BonnRoute flow as the default tool for signal routing

    Pseudopin assignment with crosstalk noise control

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